Lines Matching refs:dpcd

47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
121 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()
126 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_fast_training_cap()
128 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_fast_training_cap()
129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); in drm_dp_fast_training_cap()
133 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported()
135 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported()
136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; in drm_dp_tps3_supported()
140 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_downspread()
142 return dpcd[DP_DPCD_REV] >= 0x11 || in drm_dp_max_downspread()
143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; in drm_dp_max_downspread()
147 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps4_supported()
149 return dpcd[DP_DPCD_REV] >= 0x14 && in drm_dp_tps4_supported()
150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; in drm_dp_tps4_supported()
154 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_training_pattern_mask()
156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : in drm_dp_training_pattern_mask()
161 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_is_branch()
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; in drm_dp_is_branch()
205 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_channel_coding_supported()
207 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; in drm_dp_channel_coding_supported()
211 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_alternate_scrambler_reset_cap()
213 return dpcd[DP_EDP_CONFIGURATION_CAP] & in drm_dp_alternate_scrambler_reset_cap()
219 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_sink_can_do_video_without_timing_msa()
221 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & in drm_dp_sink_can_do_video_without_timing_msa()
479 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
492 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
494 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
496 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
499 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
501 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
504 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
507 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
510 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
512 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
515 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
519 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
524 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
528 const u8 *dpcd,
533 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
538 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
541 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
740 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
762 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],