76 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);  in otto_wdt_start()  local
79 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_start()
81 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_start()
88 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);  in otto_wdt_stop()  local
91 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_stop()
93 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_stop()
100 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);  in otto_wdt_ping()  local
102 	iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);  in otto_wdt_ping()
107 static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)  in otto_wdt_tick_ms()  argument
109 	return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);  in otto_wdt_tick_ms()
126 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);  in otto_wdt_determine_timeouts()  local
142 		tick_ms = otto_wdt_tick_ms(ctrl, prescale);  in otto_wdt_determine_timeouts()
151 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_determine_timeouts()
158 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_determine_timeouts()
161 	ctrl->wdev.timeout = timeout_ms / 1000;  in otto_wdt_determine_timeouts()
164 	ctrl->wdev.pretimeout = pretimeout_ms / 1000;  in otto_wdt_determine_timeouts()
182 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);  in otto_wdt_restart()  local
186 	disable_irq(ctrl->irq_phase1);  in otto_wdt_restart()
202 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_restart()
204 	mdelay(3 * otto_wdt_tick_ms(ctrl, 0));  in otto_wdt_restart()
211 	struct otto_wdt_ctrl *ctrl = dev_id;  in otto_wdt_phase1_isr()  local
213 	iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);  in otto_wdt_phase1_isr()
214 	dev_crit(ctrl->dev, "phase 1 timeout\n");  in otto_wdt_phase1_isr()
215 	watchdog_notify_pretimeout(&ctrl->wdev);  in otto_wdt_phase1_isr()
243 static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)  in otto_wdt_probe_clk()  argument
245 	struct clk *clk = devm_clk_get(ctrl->dev, NULL);  in otto_wdt_probe_clk()
249 		return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");  in otto_wdt_probe_clk()
253 		return dev_err_probe(ctrl->dev, ret, "Failed to enable clock\n");  in otto_wdt_probe_clk()
255 	ret = devm_add_action_or_reset(ctrl->dev, otto_wdt_clock_action, clk);  in otto_wdt_probe_clk()
259 	ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;  in otto_wdt_probe_clk()
260 	if (ctrl->clk_rate_khz == 0)  in otto_wdt_probe_clk()
261 		return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");  in otto_wdt_probe_clk()
266 static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)  in otto_wdt_probe_reset_mode()  argument
269 	const struct fwnode_handle *node = ctrl->dev->fwnode;  in otto_wdt_probe_reset_mode()
294 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe_reset_mode()
297 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe_reset_mode()
305 	struct otto_wdt_ctrl *ctrl;  in otto_wdt_probe()  local
309 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);  in otto_wdt_probe()
310 	if (!ctrl)  in otto_wdt_probe()
313 	ctrl->dev = dev;  in otto_wdt_probe()
314 	ctrl->base = devm_platform_ioremap_resource(pdev, 0);  in otto_wdt_probe()
315 	if (IS_ERR(ctrl->base))  in otto_wdt_probe()
316 		return PTR_ERR(ctrl->base);  in otto_wdt_probe()
320 			ctrl->base + OTTO_WDT_REG_INTR);  in otto_wdt_probe()
321 	iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe()
323 	ret = otto_wdt_probe_clk(ctrl);  in otto_wdt_probe()
327 	ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");  in otto_wdt_probe()
328 	if (ctrl->irq_phase1 < 0)  in otto_wdt_probe()
329 		return ctrl->irq_phase1;  in otto_wdt_probe()
331 	ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,  in otto_wdt_probe()
332 			"realtek-otto-wdt", ctrl);  in otto_wdt_probe()
336 	ret = otto_wdt_probe_reset_mode(ctrl);  in otto_wdt_probe()
340 	ctrl->wdev.parent = dev;  in otto_wdt_probe()
341 	ctrl->wdev.info = &otto_wdt_info;  in otto_wdt_probe()
342 	ctrl->wdev.ops = &otto_wdt_ops;  in otto_wdt_probe()
348 	ctrl->wdev.min_timeout = 2;  in otto_wdt_probe()
349 	max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);  in otto_wdt_probe()
350 	ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;  in otto_wdt_probe()
351 	ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);  in otto_wdt_probe()
353 	watchdog_set_drvdata(&ctrl->wdev, ctrl);  in otto_wdt_probe()
354 	watchdog_init_timeout(&ctrl->wdev, 0, dev);  in otto_wdt_probe()
355 	watchdog_stop_on_reboot(&ctrl->wdev);  in otto_wdt_probe()
356 	watchdog_set_restart_priority(&ctrl->wdev, 128);  in otto_wdt_probe()
358 	ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);  in otto_wdt_probe()
362 	return devm_watchdog_register_device(dev, &ctrl->wdev);  in otto_wdt_probe()