1 // SPDX-License-Identifier: GPL-2.0+
5  * (C) Copyright 2013 - 2014 Xilinx, Inc.
22 /* Register offsets for the Wdt device */
30 #define XWT_CSR0_EWDT1_MASK	BIT(1) /* Enable bit 1 */
33 #define XWT_CSRX_EWDT2_MASK	BIT(0) /* Enable bit 2 */
55 	ret = clk_enable(xdev->clk);  in xilinx_wdt_start()
57 		dev_err(wdd->parent, "Failed to enable clock\n");  in xilinx_wdt_start()
61 	spin_lock(&xdev->spinlock);  in xilinx_wdt_start()
63 	/* Clean previous status and enable the watchdog timer */  in xilinx_wdt_start()
64 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_start()
68 		  xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_start()
70 	iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);  in xilinx_wdt_start()
72 	spin_unlock(&xdev->spinlock);  in xilinx_wdt_start()
74 	dev_dbg(wdd->parent, "Watchdog Started!\n");  in xilinx_wdt_start()
84 	spin_lock(&xdev->spinlock);  in xilinx_wdt_stop()
86 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_stop()
89 		  xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_stop()
91 	iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);  in xilinx_wdt_stop()
93 	spin_unlock(&xdev->spinlock);  in xilinx_wdt_stop()
95 	clk_disable(xdev->clk);  in xilinx_wdt_stop()
97 	dev_dbg(wdd->parent, "Watchdog Stopped!\n");  in xilinx_wdt_stop()
107 	spin_lock(&xdev->spinlock);  in xilinx_wdt_keepalive()
109 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_keepalive()
111 	iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_keepalive()
113 	spin_unlock(&xdev->spinlock);  in xilinx_wdt_keepalive()
138 	spin_lock(&xdev->spinlock);  in xwdt_selftest()
140 	timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);  in xwdt_selftest()
141 	timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);  in xwdt_selftest()
146 		timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);  in xwdt_selftest()
149 	spin_unlock(&xdev->spinlock);  in xwdt_selftest()
164 	struct device *dev = &pdev->dev;  in xwdt_probe()
172 		return -ENOMEM;  in xwdt_probe()
174 	xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;  in xwdt_probe()
175 	xilinx_wdt_wdd->info = &xilinx_wdt_ident;  in xwdt_probe()
176 	xilinx_wdt_wdd->ops = &xilinx_wdt_ops;  in xwdt_probe()
177 	xilinx_wdt_wdd->parent = dev;  in xwdt_probe()
179 	xdev->base = devm_platform_ioremap_resource(pdev, 0);  in xwdt_probe()
180 	if (IS_ERR(xdev->base))  in xwdt_probe()
181 		return PTR_ERR(xdev->base);  in xwdt_probe()
183 	rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",  in xwdt_probe()
184 				  &xdev->wdt_interval);  in xwdt_probe()
186 		dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");  in xwdt_probe()
188 	rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",  in xwdt_probe()
192 			 "Parameter \"xlnx,wdt-enable-once\" not found\n");  in xwdt_probe()
196 	xdev->clk = devm_clk_get(dev, NULL);  in xwdt_probe()
197 	if (IS_ERR(xdev->clk)) {  in xwdt_probe()
198 		if (PTR_ERR(xdev->clk) != -ENOENT)  in xwdt_probe()
199 			return PTR_ERR(xdev->clk);  in xwdt_probe()
205 		xdev->clk = NULL;  in xwdt_probe()
207 		rc = of_property_read_u32(dev->of_node, "clock-frequency",  in xwdt_probe()
213 		pfreq = clk_get_rate(xdev->clk);  in xwdt_probe()
214 		rc = clk_prepare_enable(xdev->clk);  in xwdt_probe()
216 			dev_err(dev, "unable to enable clock\n");  in xwdt_probe()
220 					      xdev->clk);  in xwdt_probe()
226 	 * Twice of the 2^wdt_interval / freq  because the first wdt overflow is  in xwdt_probe()
227 	 * ignored (interrupt), reset is only generated at second wdt overflow  in xwdt_probe()
229 	if (pfreq && xdev->wdt_interval)  in xwdt_probe()
230 		xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /  in xwdt_probe()
233 	spin_lock_init(&xdev->spinlock);  in xwdt_probe()
246 	clk_disable(xdev->clk);  in xwdt_probe()
249 		 xilinx_wdt_wdd->timeout);  in xwdt_probe()
257  * xwdt_suspend - Suspend the device.
266 	if (watchdog_active(&xdev->xilinx_wdt_wdd))  in xwdt_suspend()
267 		xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);  in xwdt_suspend()
273  * xwdt_resume - Resume the device.
283 	if (watchdog_active(&xdev->xilinx_wdt_wdd))  in xwdt_resume()
284 		ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);  in xwdt_resume()
293 	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
294 	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },