975 	union sclk_cntl_u sclk_cntl;  member
1172 	w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;  in w100_pll_set_clk()
1173 	writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);  in w100_pll_set_clk()
1221 	w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;  in w100_pwm_setup()
1222 	w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0;  /* Pfast = 1 */  in w100_pwm_setup()
1223 	w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3;  in w100_pwm_setup()
1224 	w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0;  /* Pslow = 1 */  in w100_pwm_setup()
1225 	w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0;  in w100_pwm_setup()
1226 	w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0;    /* Dynamic */  in w100_pwm_setup()
1227 	w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0;   /* Dynamic */  in w100_pwm_setup()
1228 	w100_pwr_state.sclk_cntl.f.sclk_force_mc = 0x0;     /* Dynamic */  in w100_pwm_setup()
1229 	w100_pwr_state.sclk_cntl.f.sclk_force_extmc = 0x0;  /* Dynamic */  in w100_pwm_setup()
1230 	w100_pwr_state.sclk_cntl.f.sclk_force_cp = 0x0;     /* Dynamic */  in w100_pwm_setup()
1231 	w100_pwr_state.sclk_cntl.f.sclk_force_e2 = 0x0;     /* Dynamic */  in w100_pwm_setup()
1232 	w100_pwr_state.sclk_cntl.f.sclk_force_e3 = 0x0;     /* Dynamic */  in w100_pwm_setup()
1233 	w100_pwr_state.sclk_cntl.f.sclk_force_idct = 0x0;   /* Dynamic */  in w100_pwm_setup()
1234 	w100_pwr_state.sclk_cntl.f.sclk_force_bist = 0x0;   /* Dynamic */  in w100_pwm_setup()
1235 	w100_pwr_state.sclk_cntl.f.busy_extend_cp = 0x0;  in w100_pwm_setup()
1236 	w100_pwr_state.sclk_cntl.f.busy_extend_e2 = 0x0;  in w100_pwm_setup()
1237 	w100_pwr_state.sclk_cntl.f.busy_extend_e3 = 0x0;  in w100_pwm_setup()
1238 	w100_pwr_state.sclk_cntl.f.busy_extend_idct = 0x0;  in w100_pwm_setup()
1239 	writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);  in w100_pwm_setup()
1298 	w100_pwr_state.sclk_cntl.f.sclk_src_sel = mode->sysclk_src;  in w100_init_clocks()
1299 	w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = mode->sysclk_divider;  in w100_init_clocks()
1300 	w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider;  in w100_init_clocks()
1301 	writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);  in w100_init_clocks()