217 	tmio_iowrite16(bbisc, par->lcr + LCR_BBISC);  in tmiofb_irq()
249 	tmio_iowrite16(0, par->ccr + CCR_UGCC);  in tmiofb_hw_stop()
250 	tmio_iowrite16(0, par->lcr + LCR_GM);  in tmiofb_hw_stop()
252 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_stop()
274 	tmio_iowrite16(0x003a, par->ccr + CCR_UGCC);  in tmiofb_hw_init()
275 	tmio_iowrite16(0x003a, par->ccr + CCR_GCC);  in tmiofb_hw_init()
276 	tmio_iowrite16(0x3f00, par->ccr + CCR_USC);  in tmiofb_hw_init()
280 	tmio_iowrite16(0x0000, par->ccr + CCR_USC);  in tmiofb_hw_init()
281 	tmio_iowrite16(base >> 16, par->ccr + CCR_BASEH);  in tmiofb_hw_init()
282 	tmio_iowrite16(base, par->ccr + CCR_BASEL);  in tmiofb_hw_init()
283 	tmio_iowrite16(0x0002, par->ccr + CCR_CMD); /* base address enable */  in tmiofb_hw_init()
284 	tmio_iowrite16(0x40a8, par->ccr + CCR_VRAMRTC); /* VRAMRC, VRAMTC */  in tmiofb_hw_init()
285 	tmio_iowrite16(0x0018, par->ccr + CCR_VRAMSAC); /* VRAMSTS, VRAMAC */  in tmiofb_hw_init()
286 	tmio_iowrite16(0x0002, par->ccr + CCR_VRAMBC);  in tmiofb_hw_init()
288 	tmio_iowrite16(0x000b, par->ccr + CCR_VRAMBC);  in tmiofb_hw_init()
291 	tmio_iowrite16(base >> 16, par->lcr + LCR_CFSAH);  in tmiofb_hw_init()
292 	tmio_iowrite16(base, par->lcr + LCR_CFSAL);  in tmiofb_hw_init()
293 	tmio_iowrite16(TMIOFB_FIFO_SIZE - 1, par->lcr + LCR_CFS);  in tmiofb_hw_init()
294 	tmio_iowrite16(1, par->lcr + LCR_CFC);  in tmiofb_hw_init()
295 	tmio_iowrite16(1, par->lcr + LCR_BBIE);  in tmiofb_hw_init()
296 	tmio_iowrite16(0, par->lcr + LCR_CFWS);  in tmiofb_hw_init()
312 	tmio_iowrite16(0, par->lcr + LCR_GM);  in tmiofb_hw_mode()
314 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_mode()
318 	tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPN);  in tmiofb_hw_mode()
319 	tmio_iowrite16(0, par->lcr + LCR_GDSAH);  in tmiofb_hw_mode()
320 	tmio_iowrite16(0, par->lcr + LCR_GDSAL);  in tmiofb_hw_mode()
321 	tmio_iowrite16(info->fix.line_length >> 16, par->lcr + LCR_VHPCH);  in tmiofb_hw_mode()
322 	tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPCL);  in tmiofb_hw_mode()
323 	tmio_iowrite16(i = 0, par->lcr + LCR_HSS);  in tmiofb_hw_mode()
324 	tmio_iowrite16(i += mode->hsync_len, par->lcr + LCR_HSE);  in tmiofb_hw_mode()
325 	tmio_iowrite16(i += mode->left_margin, par->lcr + LCR_HDS);  in tmiofb_hw_mode()
326 	tmio_iowrite16(i += mode->xres + mode->right_margin, par->lcr + LCR_HT);  in tmiofb_hw_mode()
327 	tmio_iowrite16(mode->xres, par->lcr + LCR_HNP);  in tmiofb_hw_mode()
328 	tmio_iowrite16(i = 0, par->lcr + LCR_VSS);  in tmiofb_hw_mode()
329 	tmio_iowrite16(i += mode->vsync_len, par->lcr + LCR_VSE);  in tmiofb_hw_mode()
330 	tmio_iowrite16(i += mode->upper_margin, par->lcr + LCR_VDS);  in tmiofb_hw_mode()
331 	tmio_iowrite16(i += mode->yres, par->lcr + LCR_ILN);  in tmiofb_hw_mode()
332 	tmio_iowrite16(i += mode->lower_margin, par->lcr + LCR_VT);  in tmiofb_hw_mode()
333 	tmio_iowrite16(3, par->lcr + LCR_MISC); /* RGB565 mode */  in tmiofb_hw_mode()
334 	tmio_iowrite16(1, par->lcr + LCR_GM); /* VRAM enable */  in tmiofb_hw_mode()
335 	tmio_iowrite16(0x4007, par->lcr + LCR_LCDCC);  in tmiofb_hw_mode()
336 	tmio_iowrite16(3, par->lcr + LCR_SP);  /* sync polarity */  in tmiofb_hw_mode()
338 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_mode()
340 	tmio_iowrite16(0x0014, par->lcr + LCR_LCDCCRC); /* STOP_CKP */  in tmiofb_hw_mode()
342 	tmio_iowrite16(0x0015, par->lcr + LCR_LCDCCRC); /* STOP_CKP|SOFT_RESET*/  in tmiofb_hw_mode()
343 	tmio_iowrite16(0xfffa, par->lcr + LCR_VCS);  in tmiofb_hw_mode()
396 		tmio_iowrite16(*cmd >> 16, par->lcr + LCR_CMDH);  in tmiofb_acc_write()
397 		tmio_iowrite16(*cmd, par->lcr + LCR_CMDL);  in tmiofb_acc_write()