29 #define TMIOFB_ACC_CSADR(x)	(0x00000000 | ((x) & 0x001ffffe))
30 #define TMIOFB_ACC_CHPIX(x)	(0x01000000 | ((x) & 0x000003ff))
31 #define TMIOFB_ACC_CVPIX(x)	(0x02000000 | ((x) & 0x000003ff))
32 #define TMIOFB_ACC_PSADR(x)	(0x03000000 | ((x) & 0x00fffffe))
33 #define TMIOFB_ACC_PHPIX(x)	(0x04000000 | ((x) & 0x000003ff))
34 #define TMIOFB_ACC_PVPIX(x)	(0x05000000 | ((x) & 0x000003ff))
35 #define TMIOFB_ACC_PHOFS(x)	(0x06000000 | ((x) & 0x000003ff))
36 #define TMIOFB_ACC_PVOFS(x)	(0x07000000 | ((x) & 0x000003ff))
37 #define TMIOFB_ACC_POADR(x)	(0x08000000 | ((x) & 0x00fffffe))
38 #define TMIOFB_ACC_RSTR(x)	(0x09000000 | ((x) & 0x000000ff))
39 #define TMIOFB_ACC_TCLOR(x)	(0x0A000000 | ((x) & 0x0000ffff))
40 #define TMIOFB_ACC_FILL(x)	(0x0B000000 | ((x) & 0x0000ffff))
41 #define TMIOFB_ACC_DSADR(x)	(0x0C000000 | ((x) & 0x00fffffe))
42 #define TMIOFB_ACC_SSADR(x)	(0x0D000000 | ((x) & 0x00fffffe))
43 #define TMIOFB_ACC_DHPIX(x)	(0x0E000000 | ((x) & 0x000003ff))
44 #define TMIOFB_ACC_DVPIX(x)	(0x0F000000 | ((x) & 0x000003ff))
45 #define TMIOFB_ACC_SHPIX(x)	(0x10000000 | ((x) & 0x000003ff))
46 #define TMIOFB_ACC_SVPIX(x)	(0x11000000 | ((x) & 0x000003ff))
47 #define TMIOFB_ACC_LBINI(x)	(0x12000000 | ((x) & 0x0000ffff))
48 #define TMIOFB_ACC_LBK2(x)	(0x13000000 | ((x) & 0x0000ffff))
49 #define TMIOFB_ACC_SHBINI(x)	(0x14000000 | ((x) & 0x0000ffff))
50 #define TMIOFB_ACC_SHBK2(x)	(0x15000000 | ((x) & 0x0000ffff))
51 #define TMIOFB_ACC_SVBINI(x)	(0x16000000 | ((x) & 0x0000ffff))
52 #define TMIOFB_ACC_SVBK2(x)	(0x17000000 | ((x) & 0x0000ffff))
54 #define TMIOFB_ACC_CMGO		0x20000000
55 #define TMIOFB_ACC_CMGO_CEND	0x00000001
56 #define TMIOFB_ACC_CMGO_INT	0x00000002
57 #define TMIOFB_ACC_CMGO_CMOD	0x00000010
58 #define TMIOFB_ACC_CMGO_CDVRV	0x00000020
59 #define TMIOFB_ACC_CMGO_CDHRV	0x00000040
60 #define TMIOFB_ACC_CMGO_RUND	0x00008000
61 #define TMIOFB_ACC_SCGO		0x21000000
62 #define TMIOFB_ACC_SCGO_CEND	0x00000001
63 #define TMIOFB_ACC_SCGO_INT	0x00000002
64 #define TMIOFB_ACC_SCGO_ROP3	0x00000004
65 #define TMIOFB_ACC_SCGO_TRNS	0x00000008
66 #define TMIOFB_ACC_SCGO_DVRV	0x00000010
67 #define TMIOFB_ACC_SCGO_DHRV	0x00000020
68 #define TMIOFB_ACC_SCGO_SVRV	0x00000040
69 #define TMIOFB_ACC_SCGO_SHRV	0x00000080
70 #define TMIOFB_ACC_SCGO_DSTXY	0x00008000
71 #define TMIOFB_ACC_SBGO		0x22000000
72 #define TMIOFB_ACC_SBGO_CEND	0x00000001
73 #define TMIOFB_ACC_SBGO_INT	0x00000002
74 #define TMIOFB_ACC_SBGO_DVRV	0x00000010
75 #define TMIOFB_ACC_SBGO_DHRV	0x00000020
76 #define TMIOFB_ACC_SBGO_SVRV	0x00000040
77 #define TMIOFB_ACC_SBGO_SHRV	0x00000080
78 #define TMIOFB_ACC_SBGO_SBMD	0x00000100
79 #define TMIOFB_ACC_FLGO		0x23000000
80 #define TMIOFB_ACC_FLGO_CEND	0x00000001
81 #define TMIOFB_ACC_FLGO_INT	0x00000002
82 #define TMIOFB_ACC_FLGO_ROP3	0x00000004
83 #define TMIOFB_ACC_LDGO		0x24000000
84 #define TMIOFB_ACC_LDGO_CEND	0x00000001
85 #define TMIOFB_ACC_LDGO_INT	0x00000002
86 #define TMIOFB_ACC_LDGO_ROP3	0x00000004
87 #define TMIOFB_ACC_LDGO_ENDPX	0x00000008
88 #define TMIOFB_ACC_LDGO_LVRV	0x00000010
89 #define TMIOFB_ACC_LDGO_LHRV	0x00000020
90 #define TMIOFB_ACC_LDGO_LDMOD	0x00000040
100 #define CCR_CMD			0x04 /* Command				*/
101 #define CCR_REVID		0x08 /* Revision ID			*/
102 #define CCR_BASEL		0x10 /* LCD Control Reg Base Addr Low	*/
103 #define CCR_BASEH		0x12 /* LCD Control Reg Base Addr High	*/
104 #define CCR_UGCC		0x40 /* Unified Gated Clock Control	*/
105 #define CCR_GCC			0x42 /* Gated Clock Control		*/
106 #define CCR_USC			0x50 /* Unified Software Clear		*/
107 #define CCR_VRAMRTC		0x60 /* VRAM Timing Control		*/
108 				/* 0x61 VRAM Refresh Control		*/
109 #define CCR_VRAMSAC		0x62 /* VRAM Access Control		*/
110 				/* 0x63	VRAM Status			*/
111 #define CCR_VRAMBC		0x64 /* VRAM Block Control		*/
118 #define LCR_UIS			0x000 /* Unified Interrupt Status	*/
119 #define LCR_VHPN		0x008 /* VRAM Horizontal Pixel Number	*/
120 #define LCR_CFSAL		0x00a /* Command FIFO Start Address Low	*/
121 #define LCR_CFSAH		0x00c /* Command FIFO Start Address High */
122 #define LCR_CFS			0x00e /* Command FIFO Size		*/
123 #define LCR_CFWS		0x010 /* Command FIFO Writeable Size	*/
124 #define LCR_BBIE		0x012 /* BitBLT Interrupt Enable	*/
125 #define LCR_BBISC		0x014 /* BitBLT Interrupt Status and Clear */
126 #define LCR_CCS			0x016 /* Command Count Status		*/
127 #define LCR_BBES		0x018 /* BitBLT Execution Status	*/
128 #define LCR_CMDL		0x01c /* Command Low			*/
129 #define LCR_CMDH		0x01e /* Command High			*/
130 #define LCR_CFC			0x022 /* Command FIFO Clear		*/
131 #define LCR_CCIFC		0x024 /* CMOS Camera IF Control		*/
132 #define LCR_HWT			0x026 /* Hardware Test			*/
133 #define LCR_LCDCCRC		0x100 /* LCDC Clock and Reset Control	*/
134 #define LCR_LCDCC		0x102 /* LCDC Control			*/
135 #define LCR_LCDCOPC		0x104 /* LCDC Output Pin Control	*/
136 #define LCR_LCDIS		0x108 /* LCD Interrupt Status		*/
137 #define LCR_LCDIM		0x10a /* LCD Interrupt Mask		*/
138 #define LCR_LCDIE		0x10c /* LCD Interrupt Enable		*/
139 #define LCR_GDSAL		0x122 /* Graphics Display Start Address Low */
140 #define LCR_GDSAH		0x124 /* Graphics Display Start Address High */
141 #define LCR_VHPCL		0x12a /* VRAM Horizontal Pixel Count Low */
142 #define LCR_VHPCH		0x12c /* VRAM Horizontal Pixel Count High */
143 #define LCR_GM			0x12e /* Graphic Mode(VRAM access enable) */
144 #define LCR_HT			0x140 /* Horizontal Total		*/
145 #define LCR_HDS			0x142 /* Horizontal Display Start	*/
146 #define LCR_HSS			0x144 /* H-Sync Start			*/
147 #define LCR_HSE			0x146 /* H-Sync End			*/
148 #define LCR_HNP			0x14c /* Horizontal Number of Pixels	*/
149 #define LCR_VT			0x150 /* Vertical Total			*/
150 #define LCR_VDS			0x152 /* Vertical Display Start		*/
151 #define LCR_VSS			0x154 /* V-Sync Start			*/
152 #define LCR_VSE			0x156 /* V-Sync End			*/
153 #define LCR_CDLN		0x160 /* Current Display Line Number	*/
154 #define LCR_ILN			0x162 /* Interrupt Line Number		*/
155 #define LCR_SP			0x164 /* Sync Polarity			*/
156 #define LCR_MISC		0x166 /* MISC(RGB565 mode)		*/
157 #define LCR_VIHSS		0x16a /* Video Interface H-Sync Start	*/
158 #define LCR_VIVS		0x16c /* Video Interface Vertical Start	*/
159 #define LCR_VIVE		0x16e /* Video Interface Vertical End	*/
160 #define LCR_VIVSS		0x170 /* Video Interface V-Sync Start	*/
161 #define LCR_VCCIS		0x17e /* Video / CMOS Camera Interface Select */
162 #define LCR_VIDWSAL		0x180 /* VI Data Write Start Address Low */
163 #define LCR_VIDWSAH		0x182 /* VI Data Write Start Address High */
164 #define LCR_VIDRSAL		0x184 /* VI Data Read Start Address Low	*/
165 #define LCR_VIDRSAH		0x186 /* VI Data Read Start Address High */
166 #define LCR_VIPDDST		0x188 /* VI Picture Data Display Start Timing */
167 #define LCR_VIPDDET		0x186 /* VI Picture Data Display End Timing */
168 #define LCR_VIE			0x18c /* Video Interface Enable		*/
169 #define LCR_VCS			0x18e /* Video/Camera Select		*/
170 #define LCR_VPHWC		0x194 /* Video Picture Horizontal Wait Count */
171 #define LCR_VPHS		0x196 /* Video Picture Horizontal Size	*/
172 #define LCR_VPVWC		0x198 /* Video Picture Vertical Wait Count */
173 #define LCR_VPVS		0x19a /* Video Picture Vertical Size	*/
174 #define LCR_PLHPIX		0x1a0 /* PLHPIX				*/
175 #define LCR_XS			0x1a2 /* XStart				*/
176 #define LCR_XCKHW		0x1a4 /* XCK High Width			*/
177 #define LCR_STHS		0x1a8 /* STH Start			*/
178 #define LCR_VT2			0x1aa /* Vertical Total			*/
179 #define LCR_YCKSW		0x1ac /* YCK Start Wait			*/
180 #define LCR_YSTS		0x1ae /* YST Start			*/
181 #define LCR_PPOLS		0x1b0 /* #PPOL Start			*/
182 #define LCR_PRECW		0x1b2 /* PREC Width			*/
183 #define LCR_VCLKHW		0x1b4 /* VCLK High Width		*/
184 #define LCR_OC			0x1b6 /* Output Control			*/
208  * 	2000	0004	line number match(0x1ff mask???)
249 	tmio_iowrite16(0, par->ccr + CCR_UGCC);  in tmiofb_hw_stop()
250 	tmio_iowrite16(0, par->lcr + LCR_GM);  in tmiofb_hw_stop()
251 	data->lcd_set_power(dev, 0);  in tmiofb_hw_stop()
252 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_stop()
254 	return 0;  in tmiofb_hw_stop()
265 	const struct resource *nlcr = &cell->resources[0];  in tmiofb_hw_init()
274 	tmio_iowrite16(0x003a, par->ccr + CCR_UGCC);  in tmiofb_hw_init()
275 	tmio_iowrite16(0x003a, par->ccr + CCR_GCC);  in tmiofb_hw_init()
276 	tmio_iowrite16(0x3f00, par->ccr + CCR_USC);  in tmiofb_hw_init()
280 	tmio_iowrite16(0x0000, par->ccr + CCR_USC);  in tmiofb_hw_init()
283 	tmio_iowrite16(0x0002, par->ccr + CCR_CMD); /* base address enable */  in tmiofb_hw_init()
284 	tmio_iowrite16(0x40a8, par->ccr + CCR_VRAMRTC); /* VRAMRC, VRAMTC */  in tmiofb_hw_init()
285 	tmio_iowrite16(0x0018, par->ccr + CCR_VRAMSAC); /* VRAMSTS, VRAMAC */  in tmiofb_hw_init()
286 	tmio_iowrite16(0x0002, par->ccr + CCR_VRAMBC);  in tmiofb_hw_init()
288 	tmio_iowrite16(0x000b, par->ccr + CCR_VRAMBC);  in tmiofb_hw_init()
296 	tmio_iowrite16(0, par->lcr + LCR_CFWS);  in tmiofb_hw_init()
298 	return 0;  in tmiofb_hw_init()
312 	tmio_iowrite16(0, par->lcr + LCR_GM);  in tmiofb_hw_mode()
313 	data->lcd_set_power(dev, 0);  in tmiofb_hw_mode()
314 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_mode()
319 	tmio_iowrite16(0, par->lcr + LCR_GDSAH);  in tmiofb_hw_mode()
320 	tmio_iowrite16(0, par->lcr + LCR_GDSAL);  in tmiofb_hw_mode()
323 	tmio_iowrite16(i = 0, par->lcr + LCR_HSS);  in tmiofb_hw_mode()
328 	tmio_iowrite16(i = 0, par->lcr + LCR_VSS);  in tmiofb_hw_mode()
335 	tmio_iowrite16(0x4007, par->lcr + LCR_LCDCC);  in tmiofb_hw_mode()
338 	tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);  in tmiofb_hw_mode()
340 	tmio_iowrite16(0x0014, par->lcr + LCR_LCDCCRC); /* STOP_CKP */  in tmiofb_hw_mode()
342 	tmio_iowrite16(0x0015, par->lcr + LCR_LCDCCRC); /* STOP_CKP|SOFT_RESET*/  in tmiofb_hw_mode()
343 	tmio_iowrite16(0xfffa, par->lcr + LCR_VCS);  in tmiofb_hw_mode()
359 		int i = 0;  in tmiofb_acc_wait()
379 	return 0;  in tmiofb_acc_wait()
412 	int i = 0;  in tmiofb_sync()
414 	ret = tmiofb_acc_wait(fbi, 0);  in tmiofb_sync()
472 		.dx	= 0,  in tmiofb_clearscreen()
473 		.dy	= 0,  in tmiofb_clearscreen()
476 		.color	= 0,  in tmiofb_clearscreen()
500 	return 0;  in tmiofb_vblank()
509 		struct fb_vblank vblank = {0};  in tmiofb_ioctl()
515 		return 0;  in tmiofb_ioctl()
521 		return 0;  in tmiofb_ioctl()
556 	for (i = 0; i < data->num_modes; i++) {  in tmiofb_find_mode()
586 	var->xoffset = 0;  in tmiofb_check_var()
587 	var->yoffset = 0;  in tmiofb_check_var()
589 	var->grayscale = 0;  in tmiofb_check_var()
594 	var->blue.offset = 0;  in tmiofb_check_var()
596 	var->transp.offset = 0;  in tmiofb_check_var()
597 	var->transp.length = 0;  in tmiofb_check_var()
598 	var->nonstd = 0;  in tmiofb_check_var()
601 	var->rotate = 0;  in tmiofb_check_var()
602 	return 0;  in tmiofb_check_var()
620 	return 0;  in tmiofb_set_par()
631 			((red & 0xf800)) |  in tmiofb_setcolreg()
632 			((green & 0xfc00) >>  5) |  in tmiofb_setcolreg()
633 			((blue & 0xf800) >> 11);  in tmiofb_setcolreg()
634 		return 0;  in tmiofb_setcolreg()
646 	return 0;  in tmiofb_blank()
675 	struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0);  in tmiofb_probe()
677 	int irq = platform_get_irq(dev, 0);  in tmiofb_probe()
689 	if (ccr == NULL || lcr == NULL || vram == NULL || irq < 0) {  in tmiofb_probe()
743 	retval = request_irq(irq, &tmiofb_irq, 0,  in tmiofb_probe()
773 	if (retval < 0)  in tmiofb_probe()
778 	return 0;  in tmiofb_probe()
804 	int irq = platform_get_irq(dev, 0);  in tmiofb_remove()
825 	return 0;  in tmiofb_remove()
931 	int retval = 0;  in tmiofb_suspend()
963 	int retval = 0;  in tmiofb_resume()
979 	fb_set_suspend(info, 0);  in tmiofb_resume()