408 		OUTREG(DSPABASE, offset);  in intelfbhw_pan_display()
430 	OUTREG(DSPACNTR, tmp);  in intelfbhw_do_blank()
433 	OUTREG(DSPABASE, tmp);  in intelfbhw_do_blank()
465 	OUTREG(ADPA, tmp);  in intelfbhw_do_blank()
509 	OUTREG(palette_reg + (regno << 2),  in intelfbhw_setcolreg()
1296 	OUTREG(VGACNTRL, tmp);  in intelfbhw_program_mode()
1353 	OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1365 			OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1369 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1374 	OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1377 	OUTREG(DSPBCNTR, tmp);  in intelfbhw_program_mode()
1382 	OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1383 	OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1384 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1390 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1393 	OUTREG(0x61204, 0xabcd0000);  in intelfbhw_program_mode()
1398 	OUTREG(dpll_reg, tmp);  in intelfbhw_program_mode()
1401 	OUTREG(fp0_reg, *fp0);  in intelfbhw_program_mode()
1402 	OUTREG(fp1_reg, *fp1);  in intelfbhw_program_mode()
1405 	OUTREG(dpll_reg, *dpll);  in intelfbhw_program_mode()
1408 	OUTREG(DVOB, hw->dvob);  in intelfbhw_program_mode()
1409 	OUTREG(DVOC, hw->dvoc);  in intelfbhw_program_mode()
1412 	OUTREG(0x61204, 0x00000000);  in intelfbhw_program_mode()
1415 	OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1416 	OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);  in intelfbhw_program_mode()
1419 	OUTREG(hsync_reg, *hs);  in intelfbhw_program_mode()
1420 	OUTREG(hblank_reg, *hb);  in intelfbhw_program_mode()
1421 	OUTREG(htotal_reg, *ht);  in intelfbhw_program_mode()
1422 	OUTREG(vsync_reg, *vs);  in intelfbhw_program_mode()
1423 	OUTREG(vblank_reg, *vb);  in intelfbhw_program_mode()
1424 	OUTREG(vtotal_reg, *vt);  in intelfbhw_program_mode()
1425 	OUTREG(src_size_reg, *ss);  in intelfbhw_program_mode()
1430 		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);  in intelfbhw_program_mode()
1433 		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);  in intelfbhw_program_mode()
1436 		OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */  in intelfbhw_program_mode()
1439 	OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);  in intelfbhw_program_mode()
1445 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1457 			OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1458 			OUTREG(DSPACNTR,  in intelfbhw_program_mode()
1464 	OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);  in intelfbhw_program_mode()
1465 	OUTREG(DSPASTRIDE, hw->disp_a_stride);  in intelfbhw_program_mode()
1466 	OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1472 		OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1473 		OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1592 		OUTREG(FENCE + (i << 2), 0);  in reset_state()
1605 	OUTREG(PRI_RING_LENGTH, 0);  in reset_state()
1606 	OUTREG(PRI_RING_HEAD, 0);  in reset_state()
1607 	OUTREG(PRI_RING_TAIL, 0);  in reset_state()
1608 	OUTREG(PRI_RING_START, 0);  in reset_state()
1642 	OUTREG(PRI_RING_LENGTH, 0);  in intelfbhw_2d_start()
1643 	OUTREG(PRI_RING_TAIL, 0);  in intelfbhw_2d_start()
1644 	OUTREG(PRI_RING_HEAD, 0);  in intelfbhw_2d_start()
1646 	OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);  in intelfbhw_2d_start()
1647 	OUTREG(PRI_RING_LENGTH,  in intelfbhw_2d_start()
1850 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_init()
1851 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_init()
1857 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_init()
1858 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);  in intelfbhw_cursor_init()
1861 		OUTREG(CURSOR_SIZE, tmp);  in intelfbhw_cursor_init()
1880 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_hide()
1882 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_hide()
1886 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_hide()
1909 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_show()
1911 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_show()
1915 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_show()
1935 	OUTREG(CURSOR_A_POSITION, tmp);  in intelfbhw_cursor_setpos()
1938 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_setpos()
1947 	OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1948 	OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1949 	OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1950 	OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
2022 	OUTREG(PIPEASTAT, INREG(PIPEASTAT));  in intelfbhw_irq()
2027 		OUTREG(DSPABASE, dinfo->vsync.pan_offset);  in intelfbhw_irq()
2072 			OUTREG(DSPABASE, dinfo->vsync.pan_offset);  in intelfbhw_disable_irq()