Lines Matching +full:hb +full:- +full:pll +full:- +full:clock
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
73 switch (pdev->device) { in intelfbhw_get_chipset()
75 dinfo->name = "Intel(R) 830M"; in intelfbhw_get_chipset()
76 dinfo->chipset = INTEL_830M; in intelfbhw_get_chipset()
77 dinfo->mobile = 1; in intelfbhw_get_chipset()
78 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
81 dinfo->name = "Intel(R) 845G"; in intelfbhw_get_chipset()
82 dinfo->chipset = INTEL_845G; in intelfbhw_get_chipset()
83 dinfo->mobile = 0; in intelfbhw_get_chipset()
84 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
87 dinfo->mobile = 1; in intelfbhw_get_chipset()
88 dinfo->name = "Intel(R) 854"; in intelfbhw_get_chipset()
89 dinfo->chipset = INTEL_854; in intelfbhw_get_chipset()
93 dinfo->mobile = 1; in intelfbhw_get_chipset()
94 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
99 dinfo->name = "Intel(R) 855GME"; in intelfbhw_get_chipset()
100 dinfo->chipset = INTEL_855GME; in intelfbhw_get_chipset()
103 dinfo->name = "Intel(R) 855GM"; in intelfbhw_get_chipset()
104 dinfo->chipset = INTEL_855GM; in intelfbhw_get_chipset()
107 dinfo->name = "Intel(R) 852GME"; in intelfbhw_get_chipset()
108 dinfo->chipset = INTEL_852GME; in intelfbhw_get_chipset()
111 dinfo->name = "Intel(R) 852GM"; in intelfbhw_get_chipset()
112 dinfo->chipset = INTEL_852GM; in intelfbhw_get_chipset()
115 dinfo->name = "Intel(R) 852GM/855GM"; in intelfbhw_get_chipset()
116 dinfo->chipset = INTEL_85XGM; in intelfbhw_get_chipset()
121 dinfo->name = "Intel(R) 865G"; in intelfbhw_get_chipset()
122 dinfo->chipset = INTEL_865G; in intelfbhw_get_chipset()
123 dinfo->mobile = 0; in intelfbhw_get_chipset()
124 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
127 dinfo->name = "Intel(R) 915G"; in intelfbhw_get_chipset()
128 dinfo->chipset = INTEL_915G; in intelfbhw_get_chipset()
129 dinfo->mobile = 0; in intelfbhw_get_chipset()
130 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
133 dinfo->name = "Intel(R) 915GM"; in intelfbhw_get_chipset()
134 dinfo->chipset = INTEL_915GM; in intelfbhw_get_chipset()
135 dinfo->mobile = 1; in intelfbhw_get_chipset()
136 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
139 dinfo->name = "Intel(R) 945G"; in intelfbhw_get_chipset()
140 dinfo->chipset = INTEL_945G; in intelfbhw_get_chipset()
141 dinfo->mobile = 0; in intelfbhw_get_chipset()
142 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
145 dinfo->name = "Intel(R) 945GM"; in intelfbhw_get_chipset()
146 dinfo->chipset = INTEL_945GM; in intelfbhw_get_chipset()
147 dinfo->mobile = 1; in intelfbhw_get_chipset()
148 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
151 dinfo->name = "Intel(R) 945GME"; in intelfbhw_get_chipset()
152 dinfo->chipset = INTEL_945GME; in intelfbhw_get_chipset()
153 dinfo->mobile = 1; in intelfbhw_get_chipset()
154 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
157 dinfo->name = "Intel(R) 965G"; in intelfbhw_get_chipset()
158 dinfo->chipset = INTEL_965G; in intelfbhw_get_chipset()
159 dinfo->mobile = 0; in intelfbhw_get_chipset()
160 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
163 dinfo->name = "Intel(R) 965GM"; in intelfbhw_get_chipset()
164 dinfo->chipset = INTEL_965GM; in intelfbhw_get_chipset()
165 dinfo->mobile = 1; in intelfbhw_get_chipset()
166 dinfo->pll_index = PLLS_I9xx; in intelfbhw_get_chipset()
184 bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0, in intelfbhw_get_memory()
196 switch (pdev->device) { in intelfbhw_get_memory()
221 switch(pdev->device) { in intelfbhw_get_memory()
226 *stolen_size = KB(512) - KB(stolen_overhead); in intelfbhw_get_memory()
229 *stolen_size = MB(1) - KB(stolen_overhead); in intelfbhw_get_memory()
232 *stolen_size = MB(8) - KB(stolen_overhead); in intelfbhw_get_memory()
249 *stolen_size = MB(1) - KB(stolen_overhead); in intelfbhw_get_memory()
252 *stolen_size = MB(4) - KB(stolen_overhead); in intelfbhw_get_memory()
255 *stolen_size = MB(8) - KB(stolen_overhead); in intelfbhw_get_memory()
258 *stolen_size = MB(16) - KB(stolen_overhead); in intelfbhw_get_memory()
261 *stolen_size = MB(32) - KB(stolen_overhead); in intelfbhw_get_memory()
264 *stolen_size = MB(48) - KB(stolen_overhead); in intelfbhw_get_memory()
267 *stolen_size = MB(64) - KB(stolen_overhead); in intelfbhw_get_memory()
321 bytes_per_pixel = var->bits_per_pixel / 8; in intelfbhw_validate_mode()
326 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel; in intelfbhw_validate_mode()
327 if (tmp > dinfo->fb.size) { in intelfbhw_validate_mode()
330 BtoKB(tmp), BtoKB(dinfo->fb.size)); in intelfbhw_validate_mode()
335 if (var->xres - 1 > HACTIVE_MASK) { in intelfbhw_validate_mode()
337 var->xres, HACTIVE_MASK + 1); in intelfbhw_validate_mode()
340 if (var->yres - 1 > VACTIVE_MASK) { in intelfbhw_validate_mode()
342 var->yres, VACTIVE_MASK + 1); in intelfbhw_validate_mode()
345 if (var->xres < 4) { in intelfbhw_validate_mode()
346 WRN_MSG("X resolution too small (%d vs 4).\n", var->xres); in intelfbhw_validate_mode()
349 if (var->yres < 4) { in intelfbhw_validate_mode()
350 WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres); in intelfbhw_validate_mode()
355 if (var->vmode & FB_VMODE_DOUBLE) { in intelfbhw_validate_mode()
356 WRN_MSG("Mode is double-scan.\n"); in intelfbhw_validate_mode()
360 if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) { in intelfbhw_validate_mode()
365 /* Check if clock is OK. */ in intelfbhw_validate_mode()
366 tmp = 1000000000 / var->pixclock; in intelfbhw_validate_mode()
368 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n", in intelfbhw_validate_mode()
373 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n", in intelfbhw_validate_mode()
390 xoffset = ROUND_DOWN_TO(var->xoffset, 8); in intelfbhw_pan_display()
391 yoffset = var->yoffset; in intelfbhw_pan_display()
393 if ((xoffset + info->var.xres > info->var.xres_virtual) || in intelfbhw_pan_display()
394 (yoffset + info->var.yres > info->var.yres_virtual)) in intelfbhw_pan_display()
395 return -EINVAL; in intelfbhw_pan_display()
397 offset = (yoffset * dinfo->pitch) + in intelfbhw_pan_display()
398 (xoffset * info->var.bits_per_pixel) / 8; in intelfbhw_pan_display()
400 offset += dinfo->fb.offset << 12; in intelfbhw_pan_display()
402 dinfo->vsync.pan_offset = offset; in intelfbhw_pan_display()
403 if ((var->activate & FB_ACTIVATE_VBL) && in intelfbhw_pan_display()
405 dinfo->vsync.pan_display = 1; in intelfbhw_pan_display()
407 dinfo->vsync.pan_display = 0; in intelfbhw_pan_display()
437 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on); in intelfbhw_do_blank()
439 if (dinfo->cursor_on) { in intelfbhw_do_blank()
444 dinfo->cursor_on = 1; in intelfbhw_do_blank()
446 dinfo->cursor_blanked = blank; in intelfbhw_do_blank()
474 int pipe = -1; in intelfbhw_active_pipe()
476 /* keep old default behaviour - prefer PIPE_A */ in intelfbhw_active_pipe()
477 if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) { in intelfbhw_active_pipe()
478 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_active_pipe()
483 if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) { in intelfbhw_active_pipe()
484 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_active_pipe()
489 /* Impossible that no pipe is selected - return PIPE_A */ in intelfbhw_active_pipe()
490 WARN_ON(pipe == -1); in intelfbhw_active_pipe()
491 if (unlikely(pipe == -1)) in intelfbhw_active_pipe()
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
526 return -1; in intelfbhw_read_hw_state()
529 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()
530 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()
531 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()
532 hw->dpll_a = INREG(DPLL_A); in intelfbhw_read_hw_state()
533 hw->dpll_b = INREG(DPLL_B); in intelfbhw_read_hw_state()
534 hw->fpa0 = INREG(FPA0); in intelfbhw_read_hw_state()
535 hw->fpa1 = INREG(FPA1); in intelfbhw_read_hw_state()
536 hw->fpb0 = INREG(FPB0); in intelfbhw_read_hw_state()
537 hw->fpb1 = INREG(FPB1); in intelfbhw_read_hw_state()
545 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); in intelfbhw_read_hw_state()
546 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); in intelfbhw_read_hw_state()
553 hw->htotal_a = INREG(HTOTAL_A); in intelfbhw_read_hw_state()
554 hw->hblank_a = INREG(HBLANK_A); in intelfbhw_read_hw_state()
555 hw->hsync_a = INREG(HSYNC_A); in intelfbhw_read_hw_state()
556 hw->vtotal_a = INREG(VTOTAL_A); in intelfbhw_read_hw_state()
557 hw->vblank_a = INREG(VBLANK_A); in intelfbhw_read_hw_state()
558 hw->vsync_a = INREG(VSYNC_A); in intelfbhw_read_hw_state()
559 hw->src_size_a = INREG(SRC_SIZE_A); in intelfbhw_read_hw_state()
560 hw->bclrpat_a = INREG(BCLRPAT_A); in intelfbhw_read_hw_state()
561 hw->htotal_b = INREG(HTOTAL_B); in intelfbhw_read_hw_state()
562 hw->hblank_b = INREG(HBLANK_B); in intelfbhw_read_hw_state()
563 hw->hsync_b = INREG(HSYNC_B); in intelfbhw_read_hw_state()
564 hw->vtotal_b = INREG(VTOTAL_B); in intelfbhw_read_hw_state()
565 hw->vblank_b = INREG(VBLANK_B); in intelfbhw_read_hw_state()
566 hw->vsync_b = INREG(VSYNC_B); in intelfbhw_read_hw_state()
567 hw->src_size_b = INREG(SRC_SIZE_B); in intelfbhw_read_hw_state()
568 hw->bclrpat_b = INREG(BCLRPAT_B); in intelfbhw_read_hw_state()
573 hw->adpa = INREG(ADPA); in intelfbhw_read_hw_state()
574 hw->dvoa = INREG(DVOA); in intelfbhw_read_hw_state()
575 hw->dvob = INREG(DVOB); in intelfbhw_read_hw_state()
576 hw->dvoc = INREG(DVOC); in intelfbhw_read_hw_state()
577 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); in intelfbhw_read_hw_state()
578 hw->dvob_srcdim = INREG(DVOB_SRCDIM); in intelfbhw_read_hw_state()
579 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); in intelfbhw_read_hw_state()
580 hw->lvds = INREG(LVDS); in intelfbhw_read_hw_state()
585 hw->pipe_a_conf = INREG(PIPEACONF); in intelfbhw_read_hw_state()
586 hw->pipe_b_conf = INREG(PIPEBCONF); in intelfbhw_read_hw_state()
587 hw->disp_arb = INREG(DISPARB); in intelfbhw_read_hw_state()
592 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); in intelfbhw_read_hw_state()
593 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); in intelfbhw_read_hw_state()
594 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); in intelfbhw_read_hw_state()
595 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); in intelfbhw_read_hw_state()
601 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
602 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
608 hw->cursor_size = INREG(CURSOR_SIZE); in intelfbhw_read_hw_state()
613 hw->disp_a_ctrl = INREG(DSPACNTR); in intelfbhw_read_hw_state()
614 hw->disp_b_ctrl = INREG(DSPBCNTR); in intelfbhw_read_hw_state()
615 hw->disp_a_base = INREG(DSPABASE); in intelfbhw_read_hw_state()
616 hw->disp_b_base = INREG(DSPBBASE); in intelfbhw_read_hw_state()
617 hw->disp_a_stride = INREG(DSPASTRIDE); in intelfbhw_read_hw_state()
618 hw->disp_b_stride = INREG(DSPBSTRIDE); in intelfbhw_read_hw_state()
623 hw->vgacntrl = INREG(VGACNTRL); in intelfbhw_read_hw_state()
628 hw->add_id = INREG(ADD_ID); in intelfbhw_read_hw_state()
634 hw->swf0x[i] = INREG(SWF00 + (i << 2)); in intelfbhw_read_hw_state()
635 hw->swf1x[i] = INREG(SWF10 + (i << 2)); in intelfbhw_read_hw_state()
637 hw->swf3x[i] = INREG(SWF30 + (i << 2)); in intelfbhw_read_hw_state()
641 hw->fence[i] = INREG(FENCE + (i << 2)); in intelfbhw_read_hw_state()
643 hw->instpm = INREG(INSTPM); in intelfbhw_read_hw_state()
644 hw->mem_mode = INREG(MEM_MODE); in intelfbhw_read_hw_state()
645 hw->fw_blc_0 = INREG(FW_BLC_0); in intelfbhw_read_hw_state()
646 hw->fw_blc_1 = INREG(FW_BLC_1); in intelfbhw_read_hw_state()
648 hw->hwstam = INREG16(HWSTAM); in intelfbhw_read_hw_state()
649 hw->ier = INREG16(IER); in intelfbhw_read_hw_state()
650 hw->iir = INREG16(IIR); in intelfbhw_read_hw_state()
651 hw->imr = INREG16(IMR); in intelfbhw_read_hw_state()
667 struct pll_min_max *pll = &plls[index]; in calc_vclock() local
672 vco = pll->ref_clk * m / n; in calc_vclock()
715 int index = dinfo->pll_index; in intelfbhw_print_hw_state()
722 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); in intelfbhw_print_hw_state()
723 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); in intelfbhw_print_hw_state()
724 printk(" VGAPD: 0x%08x\n", hw->vga_pd); in intelfbhw_print_hw_state()
725 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
726 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
729 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); in intelfbhw_print_hw_state()
733 printk(" VGA0: clock is %d\n", in intelfbhw_print_hw_state()
736 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
737 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
740 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); in intelfbhw_print_hw_state()
743 printk(" VGA1: clock is %d\n", in intelfbhw_print_hw_state()
746 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); in intelfbhw_print_hw_state()
747 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); in intelfbhw_print_hw_state()
748 printk(" FPA0: 0x%08x\n", hw->fpa0); in intelfbhw_print_hw_state()
749 printk(" FPA1: 0x%08x\n", hw->fpa1); in intelfbhw_print_hw_state()
750 printk(" FPB0: 0x%08x\n", hw->fpb0); in intelfbhw_print_hw_state()
751 printk(" FPB1: 0x%08x\n", hw->fpb1); in intelfbhw_print_hw_state()
753 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
754 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
757 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); in intelfbhw_print_hw_state()
761 printk(" PLLA0: clock is %d\n", in intelfbhw_print_hw_state()
764 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
765 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
766 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
768 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); in intelfbhw_print_hw_state()
772 printk(" PLLA1: clock is %d\n", in intelfbhw_print_hw_state()
778 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); in intelfbhw_print_hw_state()
781 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); in intelfbhw_print_hw_state()
784 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); in intelfbhw_print_hw_state()
785 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); in intelfbhw_print_hw_state()
786 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); in intelfbhw_print_hw_state()
787 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); in intelfbhw_print_hw_state()
788 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); in intelfbhw_print_hw_state()
789 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); in intelfbhw_print_hw_state()
790 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); in intelfbhw_print_hw_state()
791 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); in intelfbhw_print_hw_state()
792 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); in intelfbhw_print_hw_state()
793 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); in intelfbhw_print_hw_state()
794 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); in intelfbhw_print_hw_state()
795 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); in intelfbhw_print_hw_state()
796 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); in intelfbhw_print_hw_state()
797 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); in intelfbhw_print_hw_state()
798 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); in intelfbhw_print_hw_state()
799 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); in intelfbhw_print_hw_state()
801 printk(" ADPA: 0x%08x\n", hw->adpa); in intelfbhw_print_hw_state()
802 printk(" DVOA: 0x%08x\n", hw->dvoa); in intelfbhw_print_hw_state()
803 printk(" DVOB: 0x%08x\n", hw->dvob); in intelfbhw_print_hw_state()
804 printk(" DVOC: 0x%08x\n", hw->dvoc); in intelfbhw_print_hw_state()
805 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); in intelfbhw_print_hw_state()
806 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); in intelfbhw_print_hw_state()
807 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); in intelfbhw_print_hw_state()
808 printk(" LVDS: 0x%08x\n", hw->lvds); in intelfbhw_print_hw_state()
810 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); in intelfbhw_print_hw_state()
811 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); in intelfbhw_print_hw_state()
812 printk(" DISPARB: 0x%08x\n", hw->disp_arb); in intelfbhw_print_hw_state()
814 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); in intelfbhw_print_hw_state()
815 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); in intelfbhw_print_hw_state()
816 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); in intelfbhw_print_hw_state()
817 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); in intelfbhw_print_hw_state()
821 printk("0x%08x", hw->cursor_a_palette[i]); in intelfbhw_print_hw_state()
828 printk("0x%08x", hw->cursor_b_palette[i]); in intelfbhw_print_hw_state()
834 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); in intelfbhw_print_hw_state()
836 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); in intelfbhw_print_hw_state()
837 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); in intelfbhw_print_hw_state()
838 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); in intelfbhw_print_hw_state()
839 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); in intelfbhw_print_hw_state()
840 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); in intelfbhw_print_hw_state()
841 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); in intelfbhw_print_hw_state()
843 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); in intelfbhw_print_hw_state()
844 printk(" ADD_ID: 0x%08x\n", hw->add_id); in intelfbhw_print_hw_state()
848 hw->swf0x[i]); in intelfbhw_print_hw_state()
852 hw->swf1x[i]); in intelfbhw_print_hw_state()
856 hw->swf3x[i]); in intelfbhw_print_hw_state()
860 hw->fence[i]); in intelfbhw_print_hw_state()
862 printk(" INSTPM 0x%08x\n", hw->instpm); in intelfbhw_print_hw_state()
863 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); in intelfbhw_print_hw_state()
864 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); in intelfbhw_print_hw_state()
865 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); in intelfbhw_print_hw_state()
867 printk(" HWSTAM 0x%04x\n", hw->hwstam); in intelfbhw_print_hw_state()
868 printk(" IER 0x%04x\n", hw->ier); in intelfbhw_print_hw_state()
869 printk(" IIR 0x%04x\n", hw->iir); in intelfbhw_print_hw_state()
870 printk(" IMR 0x%04x\n", hw->imr); in intelfbhw_print_hw_state()
883 struct pll_min_max *pll = &plls[index]; in splitm() local
885 /* no point optimising too much - brute force m */ in splitm()
886 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { in splitm()
887 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { in splitm()
904 struct pll_min_max *pll = &plls[index]; in splitp() local
920 p1 = (p / (1 << (p2 + 1))) - 2; in splitp()
921 if (p % 4 == 0 && p1 < pll->min_p1) { in splitp()
923 p1 = (p / (1 << (p2 + 1))) - 2; in splitp()
925 if (p1 < pll->min_p1 || p1 > pll->max_p1 || in splitp()
935 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, in calc_pll_params() argument
943 struct pll_min_max *pll = &plls[index]; in calc_pll_params() local
945 DBG_MSG("Clock is %d\n", clock); in calc_pll_params()
947 div_max = pll->max_vco / clock; in calc_pll_params()
949 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi; in calc_pll_params()
952 if (p_min < pll->min_p) in calc_pll_params()
953 p_min = pll->min_p; in calc_pll_params()
954 if (p_max > pll->max_p) in calc_pll_params()
955 p_max = pll->max_p; in calc_pll_params()
957 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc); in calc_pll_params()
966 n = pll->min_n; in calc_pll_params()
967 f_vco = clock * p; in calc_pll_params()
970 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk; in calc_pll_params()
971 if (m < pll->min_m) in calc_pll_params()
972 m = pll->min_m + 1; in calc_pll_params()
973 if (m > pll->max_m) in calc_pll_params()
974 m = pll->max_m - 1; in calc_pll_params()
975 for (testm = m - 1; testm <= m; testm++) { in calc_pll_params()
982 if (clock > f_out) in calc_pll_params()
983 f_err = clock - f_out; in calc_pll_params()
985 f_err = f_out - clock + 1; in calc_pll_params()
995 } while ((n <= pll->max_n) && (f_out >= clock)); in calc_pll_params()
1000 WRN_MSG("cannot find parameters for clock %d\n", clock); in calc_pll_params()
1008 n1 = n - 2; in calc_pll_params()
1044 u32 m1, m2, n, p1, p2, clock_target, clock; in intelfbhw_mode_to_hw() local
1048 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf; in intelfbhw_mode_to_hw() local
1054 hw->vgacntrl |= VGA_DISABLE; in intelfbhw_mode_to_hw()
1058 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1059 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw()
1060 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
1061 hs = &hw->hsync_b; in intelfbhw_mode_to_hw()
1062 hb = &hw->hblank_b; in intelfbhw_mode_to_hw()
1063 ht = &hw->htotal_b; in intelfbhw_mode_to_hw()
1064 vs = &hw->vsync_b; in intelfbhw_mode_to_hw()
1065 vb = &hw->vblank_b; in intelfbhw_mode_to_hw()
1066 vt = &hw->vtotal_b; in intelfbhw_mode_to_hw()
1067 ss = &hw->src_size_b; in intelfbhw_mode_to_hw()
1068 pipe_conf = &hw->pipe_b_conf; in intelfbhw_mode_to_hw()
1070 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
1071 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw()
1072 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
1073 hs = &hw->hsync_a; in intelfbhw_mode_to_hw()
1074 hb = &hw->hblank_a; in intelfbhw_mode_to_hw()
1075 ht = &hw->htotal_a; in intelfbhw_mode_to_hw()
1076 vs = &hw->vsync_a; in intelfbhw_mode_to_hw()
1077 vb = &hw->vblank_a; in intelfbhw_mode_to_hw()
1078 vt = &hw->vtotal_a; in intelfbhw_mode_to_hw()
1079 ss = &hw->src_size_a; in intelfbhw_mode_to_hw()
1080 pipe_conf = &hw->pipe_a_conf; in intelfbhw_mode_to_hw()
1084 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; in intelfbhw_mode_to_hw()
1087 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? in intelfbhw_mode_to_hw()
1089 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? in intelfbhw_mode_to_hw()
1091 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
1093 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
1097 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
1098 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
1101 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_mode_to_hw()
1102 hw->adpa |= ADPA_DPMS_D0; in intelfbhw_mode_to_hw()
1104 hw->adpa |= ADPA_DAC_ENABLE; in intelfbhw_mode_to_hw()
1110 /* Desired clock in kHz */ in intelfbhw_mode_to_hw()
1111 clock_target = 1000000000 / var->pixclock; in intelfbhw_mode_to_hw()
1113 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, in intelfbhw_mode_to_hw()
1114 &n, &p1, &p2, &clock)) { in intelfbhw_mode_to_hw()
1120 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter")) in intelfbhw_mode_to_hw()
1122 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter")) in intelfbhw_mode_to_hw()
1124 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) in intelfbhw_mode_to_hw()
1126 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) in intelfbhw_mode_to_hw()
1128 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) in intelfbhw_mode_to_hw()
1137 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT; in intelfbhw_mode_to_hw()
1146 hw->dvob &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
1147 hw->dvoc &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
1150 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; in intelfbhw_mode_to_hw()
1151 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
1152 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; in intelfbhw_mode_to_hw()
1155 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
1158 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; in intelfbhw_mode_to_hw()
1161 hw->disp_a_ctrl |= DISPPLANE_16BPP; in intelfbhw_mode_to_hw()
1164 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; in intelfbhw_mode_to_hw()
1167 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
1168 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
1171 hactive = var->xres; in intelfbhw_mode_to_hw()
1172 hsync_start = hactive + var->right_margin; in intelfbhw_mode_to_hw()
1173 hsync_end = hsync_start + var->hsync_len; in intelfbhw_mode_to_hw()
1174 htotal = hsync_end + var->left_margin; in intelfbhw_mode_to_hw()
1182 vactive = var->yres; in intelfbhw_mode_to_hw()
1183 if (var->vmode & FB_VMODE_INTERLACED) in intelfbhw_mode_to_hw()
1184 vactive--; /* the chip adds 2 halflines automatically */ in intelfbhw_mode_to_hw()
1185 vsync_start = vactive + var->lower_margin; in intelfbhw_mode_to_hw()
1186 vsync_end = vsync_start + var->vsync_len; in intelfbhw_mode_to_hw()
1187 vtotal = vsync_end + var->upper_margin; in intelfbhw_mode_to_hw()
1196 hactive--; in intelfbhw_mode_to_hw()
1199 hsync_start--; in intelfbhw_mode_to_hw()
1202 hsync_end--; in intelfbhw_mode_to_hw()
1205 htotal--; in intelfbhw_mode_to_hw()
1208 hblank_start--; in intelfbhw_mode_to_hw()
1211 hblank_end--; in intelfbhw_mode_to_hw()
1215 vactive--; in intelfbhw_mode_to_hw()
1218 vsync_start--; in intelfbhw_mode_to_hw()
1221 vsync_end--; in intelfbhw_mode_to_hw()
1224 vtotal--; in intelfbhw_mode_to_hw()
1227 vblank_start--; in intelfbhw_mode_to_hw()
1230 vblank_end--; in intelfbhw_mode_to_hw()
1235 *hb = (hblank_start << HBLANKSTART_SHIFT) | in intelfbhw_mode_to_hw()
1246 hw->disp_a_stride = dinfo->pitch; in intelfbhw_mode_to_hw()
1247 DBG_MSG("pitch is %d\n", hw->disp_a_stride); in intelfbhw_mode_to_hw()
1249 hw->disp_a_base = hw->disp_a_stride * var->yoffset + in intelfbhw_mode_to_hw()
1250 var->xoffset * var->bits_per_pixel / 8; in intelfbhw_mode_to_hw()
1252 hw->disp_a_base += dinfo->fb.offset << 12; in intelfbhw_mode_to_hw()
1257 if (hw->disp_a_stride % stride_alignment != 0) { in intelfbhw_mode_to_hw()
1259 hw->disp_a_stride, stride_alignment); in intelfbhw_mode_to_hw()
1263 /* Set the palette to 8-bit mode. */ in intelfbhw_mode_to_hw()
1266 if (var->vmode & FB_VMODE_INTERLACED) in intelfbhw_mode_to_hw()
1274 /* Program a (non-VGA) video mode. */
1280 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss; in intelfbhw_program_mode() local
1298 dinfo->pipe = intelfbhw_active_pipe(hw); in intelfbhw_program_mode()
1300 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()
1301 dpll = &hw->dpll_b; in intelfbhw_program_mode()
1302 fp0 = &hw->fpb0; in intelfbhw_program_mode()
1303 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1304 pipe_conf = &hw->pipe_b_conf; in intelfbhw_program_mode()
1305 hs = &hw->hsync_b; in intelfbhw_program_mode()
1306 hb = &hw->hblank_b; in intelfbhw_program_mode()
1307 ht = &hw->htotal_b; in intelfbhw_program_mode()
1308 vs = &hw->vsync_b; in intelfbhw_program_mode()
1309 vb = &hw->vblank_b; in intelfbhw_program_mode()
1310 vt = &hw->vtotal_b; in intelfbhw_program_mode()
1311 ss = &hw->src_size_b; in intelfbhw_program_mode()
1325 dpll = &hw->dpll_a; in intelfbhw_program_mode()
1326 fp0 = &hw->fpa0; in intelfbhw_program_mode()
1327 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1328 pipe_conf = &hw->pipe_a_conf; in intelfbhw_program_mode()
1329 hs = &hw->hsync_a; in intelfbhw_program_mode()
1330 hb = &hw->hblank_a; in intelfbhw_program_mode()
1331 ht = &hw->htotal_a; in intelfbhw_program_mode()
1332 vs = &hw->vsync_a; in intelfbhw_program_mode()
1333 vb = &hw->vblank_a; in intelfbhw_program_mode()
1334 vt = &hw->vtotal_a; in intelfbhw_program_mode()
1335 ss = &hw->src_size_a; in intelfbhw_program_mode()
1392 /* do some funky magic - xyzzy */ in intelfbhw_program_mode()
1395 /* turn off PLL */ in intelfbhw_program_mode()
1400 /* Set PLL parameters */ in intelfbhw_program_mode()
1404 /* Enable PLL */ in intelfbhw_program_mode()
1408 OUTREG(DVOB, hw->dvob); in intelfbhw_program_mode()
1409 OUTREG(DVOC, hw->dvoc); in intelfbhw_program_mode()
1416 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); in intelfbhw_program_mode()
1420 OUTREG(hblank_reg, *hb); in intelfbhw_program_mode()
1427 switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED | in intelfbhw_program_mode()
1435 default: /* non-interlaced */ in intelfbhw_program_mode()
1448 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) { in intelfbhw_program_mode()
1459 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode()
1464 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode()
1465 OUTREG(DSPASTRIDE, hw->disp_a_stride); in intelfbhw_program_mode()
1466 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()
1473 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()
1488 if (dinfo->ring_tail >= dinfo->ring_head) in get_ring_space()
1489 ring_space = dinfo->ring.size - in get_ring_space()
1490 (dinfo->ring_tail - dinfo->ring_head); in get_ring_space()
1492 ring_space = dinfo->ring_head - dinfo->ring_tail; in get_ring_space()
1495 ring_space -= RING_MIN_FREE; in get_ring_space()
1513 while (dinfo->ring_space < n) { in wait_ring()
1514 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; in wait_ring()
1515 dinfo->ring_space = get_ring_space(dinfo); in wait_ring()
1517 if (dinfo->ring_head != last_head) { in wait_ring()
1519 last_head = dinfo->ring_head; in wait_ring()
1532 dinfo->ring_space, n); in wait_ring()
1533 WRN_MSG("lockup - turning off hardware " in wait_ring()
1535 dinfo->ring_lockup = 1; in wait_ring()
1558 if (!dinfo->accel) in intelfbhw_do_sync()
1567 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE); in intelfbhw_do_sync()
1568 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE; in intelfbhw_do_sync()
1577 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; in refresh_ring()
1578 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; in refresh_ring()
1579 dinfo->ring_space = get_ring_space(dinfo); in refresh_ring()
1616 dinfo->accel, dinfo->ring_active); in intelfbhw_2d_stop()
1619 if (!dinfo->accel) in intelfbhw_2d_stop()
1622 dinfo->ring_active = 0; in intelfbhw_2d_stop()
1635 dinfo->accel, dinfo->ring_active); in intelfbhw_2d_start()
1638 if (!dinfo->accel) in intelfbhw_2d_start()
1646 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK); in intelfbhw_2d_start()
1648 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) | in intelfbhw_2d_start()
1651 dinfo->ring_active = 1; in intelfbhw_2d_start()
1666 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8)); in intelfbhw_do_fillrect()
1694 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head, in intelfbhw_do_fillrect()
1695 dinfo->ring_tail, dinfo->ring_space); in intelfbhw_do_fillrect()
1706 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n", in intelfbhw_do_bitblt()
1711 br09 = dinfo->fb_start; in intelfbhw_do_bitblt()
1713 br12 = dinfo->fb_start; in intelfbhw_do_bitblt()
1771 /* Src data is packaged a dword (32-bit) at a time. */ in intelfbhw_do_drawglyph()
1782 br09 = dinfo->fb_start; in intelfbhw_do_drawglyph()
1812 while (ndwords--) { in intelfbhw_do_drawglyph()
1819 if (ix == iw && iy != (h-1)) { in intelfbhw_do_drawglyph()
1842 if (dinfo->mobile || IS_I9XX(dinfo)) { in intelfbhw_cursor_init()
1843 if (!dinfo->cursor.physical) in intelfbhw_cursor_init()
1851 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); in intelfbhw_cursor_init()
1858 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12); in intelfbhw_cursor_init()
1873 dinfo->cursor_on = 0; in intelfbhw_cursor_hide()
1874 if (dinfo->mobile || IS_I9XX(dinfo)) { in intelfbhw_cursor_hide()
1875 if (!dinfo->cursor.physical) in intelfbhw_cursor_hide()
1882 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); in intelfbhw_cursor_hide()
1898 dinfo->cursor_on = 1; in intelfbhw_cursor_show()
1900 if (dinfo->cursor_blanked) in intelfbhw_cursor_show()
1903 if (dinfo->mobile || IS_I9XX(dinfo)) { in intelfbhw_cursor_show()
1904 if (!dinfo->cursor.physical) in intelfbhw_cursor_show()
1911 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); in intelfbhw_cursor_show()
1930 * completely off-screen, and that x, y are always >= 0. in intelfbhw_cursor_setpos()
1938 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); in intelfbhw_cursor_setpos()
1956 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; in intelfbhw_cursor_load()
1964 if (!dinfo->cursor.virtual) in intelfbhw_cursor_load()
1969 for (i = height; i--; ) { in intelfbhw_cursor_load()
1984 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; in intelfbhw_cursor_reset()
1991 if (!dinfo->cursor.virtual) in intelfbhw_cursor_reset()
1994 for (i = 64; i--; ) { in intelfbhw_cursor_reset()
2008 spin_lock(&dinfo->int_lock); in intelfbhw_irq()
2011 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED) in intelfbhw_irq()
2014 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ in intelfbhw_irq()
2017 spin_unlock(&dinfo->int_lock); in intelfbhw_irq()
2021 /* clear status bits 0-15 ASAP and don't touch bits 16-31 */ in intelfbhw_irq()
2025 if (dinfo->vsync.pan_display) { in intelfbhw_irq()
2026 dinfo->vsync.pan_display = 0; in intelfbhw_irq()
2027 OUTREG(DSPABASE, dinfo->vsync.pan_offset); in intelfbhw_irq()
2030 dinfo->vsync.count++; in intelfbhw_irq()
2031 wake_up_interruptible(&dinfo->vsync.wait); in intelfbhw_irq()
2033 spin_unlock(&dinfo->int_lock); in intelfbhw_irq()
2041 if (!test_and_set_bit(0, &dinfo->irq_flags)) { in intelfbhw_enable_irq()
2042 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED, in intelfbhw_enable_irq()
2044 clear_bit(0, &dinfo->irq_flags); in intelfbhw_enable_irq()
2045 return -EINVAL; in intelfbhw_enable_irq()
2048 spin_lock_irq(&dinfo->int_lock); in intelfbhw_enable_irq()
2052 spin_lock_irq(&dinfo->int_lock); in intelfbhw_enable_irq()
2054 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED) in intelfbhw_enable_irq()
2057 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ in intelfbhw_enable_irq()
2063 spin_unlock_irq(&dinfo->int_lock); in intelfbhw_enable_irq()
2069 if (test_and_clear_bit(0, &dinfo->irq_flags)) { in intelfbhw_disable_irq()
2070 if (dinfo->vsync.pan_display) { in intelfbhw_disable_irq()
2071 dinfo->vsync.pan_display = 0; in intelfbhw_disable_irq()
2072 OUTREG(DSPABASE, dinfo->vsync.pan_offset); in intelfbhw_disable_irq()
2074 spin_lock_irq(&dinfo->int_lock); in intelfbhw_disable_irq()
2080 spin_unlock_irq(&dinfo->int_lock); in intelfbhw_disable_irq()
2082 free_irq(dinfo->pdev->irq, dinfo); in intelfbhw_disable_irq()
2094 vsync = &dinfo->vsync; in intelfbhw_wait_for_vsync()
2097 return -ENODEV; in intelfbhw_wait_for_vsync()
2104 count = vsync->count; in intelfbhw_wait_for_vsync()
2105 ret = wait_event_interruptible_timeout(vsync->wait, in intelfbhw_wait_for_vsync()
2106 count != vsync->count, HZ / 10); in intelfbhw_wait_for_vsync()
2111 return -ETIMEDOUT; in intelfbhw_wait_for_vsync()