170 	TVPADDRW = 0x00,	/* 0  Palette/Cursor RAM Write Address/Index */  enumerator
621 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
623 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
625 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
627 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
630 	par->cmap_regs[TVPADDRW] = TVPIRTCC;		eieio();  in set_imstt_regvals_tvp()
632 	par->cmap_regs[TVPADDRW] = TVPIRMXC;		eieio();  in set_imstt_regvals_tvp()
634 	par->cmap_regs[TVPADDRW] = TVPIRMIC;		eieio();  in set_imstt_regvals_tvp()
637 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
639 	par->cmap_regs[TVPADDRW] = TVPIRLPD;		eieio();  in set_imstt_regvals_tvp()
642 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
644 	par->cmap_regs[TVPADDRW] = TVPIRMLC;		eieio();  in set_imstt_regvals_tvp()
647 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
649 	par->cmap_regs[TVPADDRW] = TVPIRLPD;		eieio();  in set_imstt_regvals_tvp()
762 		par->cmap_regs[TVPADDRW] = TVPIRTCC;	eieio();  in set_555()
775 		par->cmap_regs[TVPADDRW] = TVPIRTCC;	eieio();  in set_565()
1127 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1129 		par->cmap_regs[TVPADDRW] = 0;		eieio();
1136 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1140 				par->cmap_regs[TVPADDRW] = x + y * 8;	eieio();
1143 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1147 				par->cmap_regs[TVPADDRW] = x + y * 8;	eieio();
1181 			par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1190 			par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1385 			par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;  in init_imstt()