1 // SPDX-License-Identifier: GPL-2.0-or-later
4  *   -- Geode GX1 display controller
58 		return -ENOMEM;  in gx1_frame_buffer_size()
74 	return dram_size - fb_base;  in gx1_frame_buffer_size()
79 	struct geodefb_par *par = info->par;  in gx1_set_mode()
85 	readl(par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
86 	writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
88 	gcfg = readl(par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
89 	tcfg = readl(par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
91 	/* Blank the display and disable the timing generator. */  in gx1_set_mode()
93 	writel(tcfg, par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
98 	/* Disable FIFO load and compression. */  in gx1_set_mode()
100 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
104 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
106 	par->vid_ops->set_dclk(info);  in gx1_set_mode()
110 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
131 	writel(0, par->dc_regs + DC_FB_ST_OFFSET);  in gx1_set_mode()
134 	writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);  in gx1_set_mode()
135 	writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,  in gx1_set_mode()
136 	       par->dc_regs + DC_BUF_SIZE);  in gx1_set_mode()
140 	if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;  in gx1_set_mode()
142 	/* Enable timing generator, sync and FP data. */  in gx1_set_mode()
147 	hactive = info->var.xres;  in gx1_set_mode()
149 	hsyncstart = hblankstart + info->var.right_margin;  in gx1_set_mode()
150 	hsyncend =  hsyncstart + info->var.hsync_len;  in gx1_set_mode()
151 	hblankend = hsyncend + info->var.left_margin;  in gx1_set_mode()
154 	vactive = info->var.yres;  in gx1_set_mode()
156 	vsyncstart = vblankstart + info->var.lower_margin;  in gx1_set_mode()
157 	vsyncend =  vsyncstart + info->var.vsync_len;  in gx1_set_mode()
158 	vblankend = vsyncend + info->var.upper_margin;  in gx1_set_mode()
161 	val = (hactive - 1) | ((htotal - 1) << 16);  in gx1_set_mode()
162 	writel(val, par->dc_regs + DC_H_TIMING_1);  in gx1_set_mode()
163 	val = (hblankstart - 1) | ((hblankend - 1) << 16);  in gx1_set_mode()
164 	writel(val, par->dc_regs + DC_H_TIMING_2);  in gx1_set_mode()
165 	val = (hsyncstart - 1) | ((hsyncend - 1) << 16);  in gx1_set_mode()
166 	writel(val, par->dc_regs + DC_H_TIMING_3);  in gx1_set_mode()
167 	writel(val, par->dc_regs + DC_FP_H_TIMING);  in gx1_set_mode()
168 	val = (vactive - 1) | ((vtotal - 1) << 16);  in gx1_set_mode()
169 	writel(val, par->dc_regs + DC_V_TIMING_1);  in gx1_set_mode()
170 	val = (vblankstart - 1) | ((vblankend - 1) << 16);  in gx1_set_mode()
171 	writel(val, par->dc_regs + DC_V_TIMING_2);  in gx1_set_mode()
172 	val = (vsyncstart - 1) | ((vsyncend - 1) << 16);  in gx1_set_mode()
173 	writel(val, par->dc_regs + DC_V_TIMING_3);  in gx1_set_mode()
174 	val = (vsyncstart - 2) | ((vsyncend - 2) << 16);  in gx1_set_mode()
175 	writel(val, par->dc_regs + DC_FP_V_TIMING);  in gx1_set_mode()
178 	writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);  in gx1_set_mode()
179 	writel(tcfg, par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
181 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
183 	par->vid_ops->configure_display(info);  in gx1_set_mode()
186 	writel(0, par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
195 	struct geodefb_par *par = info->par;  in gx1_set_hw_palette_reg()
198 	/* Hardware palette is in RGB 6-6-6 format. */  in gx1_set_hw_palette_reg()
203 	writel(regno, par->dc_regs + DC_PAL_ADDRESS);  in gx1_set_hw_palette_reg()
204 	writel(val, par->dc_regs + DC_PAL_DATA);  in gx1_set_hw_palette_reg()