Lines Matching +full:sync +full:- +full:on +full:- +full:green +full:- +full:active
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2008-2009 MontaVista Software Inc.
4 * Copyright (C) 2008-2009 Texas Instruments Inc
6 * Based on the LCD driver for TI Avalanche processors written by
12 #include <linux/dma-mapping.h>
27 #include <video/da8xx-fb.h>
113 /* Clock registers available only on Version 2 */
200 .sync = FB_SYNC_CLK_INVERT,
214 .sync = 0,
229 .sync = 0,
233 /* Densitron 84-0023-001T */
234 .name = "Densitron_84-0023-001T",
244 .sync = 0,
314 start = par->dma_start; in lcd_blit()
315 end = par->dma_end; in lcd_blit()
334 start = par->p_palette_base; in lcd_blit()
335 end = start + par->palette_sz - 1; in lcd_blit()
410 reg |= (((back_porch-1) & 0xff) << 24) in lcd_cfg_horizontal_sync()
411 | (((front_porch-1) & 0xff) << 16) in lcd_cfg_horizontal_sync()
412 | (((pulse_width-1) & 0x3f) << 10); in lcd_cfg_horizontal_sync()
424 reg |= ((front_porch-1) & 0x300) >> 8; in lcd_cfg_horizontal_sync()
425 reg |= ((back_porch-1) & 0x300) >> 4; in lcd_cfg_horizontal_sync()
426 reg |= ((pulse_width-1) & 0x3c0) << 21; in lcd_cfg_horizontal_sync()
439 | (((pulse_width-1) & 0x3f) << 10); in lcd_cfg_vertical_sync()
453 switch (cfg->panel_shade) { in lcd_cfg_display()
456 if (cfg->mono_8bit_mode) in lcd_cfg_display()
461 if (cfg->tft_alt_mode) in lcd_cfg_display()
467 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); in lcd_cfg_display()
468 if (cfg->bpp == 12 && cfg->stn_565_mode) in lcd_cfg_display()
473 return -EINVAL; in lcd_cfg_display()
491 if (cfg->sync_edge) in lcd_cfg_display()
496 if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0) in lcd_cfg_display()
501 if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0) in lcd_cfg_display()
517 return -EINVAL; in lcd_cfg_frame_buffer()
538 reg |= ((width >> 4) - 1) << 4; in lcd_cfg_frame_buffer()
540 width = (width >> 4) - 1; in lcd_cfg_frame_buffer()
548 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); in lcd_cfg_frame_buffer()
554 reg |= ((height - 1) & 0x400) << 16; in lcd_cfg_frame_buffer()
563 par->palette_sz = 16 * 2; in lcd_cfg_frame_buffer()
579 par->palette_sz = 256 * 2; in lcd_cfg_frame_buffer()
583 return -EINVAL; in lcd_cfg_frame_buffer()
591 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
592 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, in fb_setcolreg() argument
596 struct da8xx_fb_par *par = info->par; in fb_setcolreg()
597 unsigned short *palette = (unsigned short *) par->v_palette_base; in fb_setcolreg()
604 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) in fb_setcolreg()
607 if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) in fb_setcolreg()
608 return -EINVAL; in fb_setcolreg()
610 switch (info->fix.visual) { in fb_setcolreg()
612 red = CNVT_TOHW(red, info->var.red.length); in fb_setcolreg()
613 green = CNVT_TOHW(green, info->var.green.length); in fb_setcolreg()
614 blue = CNVT_TOHW(blue, info->var.blue.length); in fb_setcolreg()
617 switch (info->var.bits_per_pixel) { in fb_setcolreg()
620 return -EINVAL; in fb_setcolreg()
622 if (info->var.grayscale) { in fb_setcolreg()
626 green >>= 8; in fb_setcolreg()
630 pal |= green & 0x00f0; in fb_setcolreg()
640 green >>= 8; in fb_setcolreg()
644 pal |= (green & 0x00f0); in fb_setcolreg()
657 if (info->fix.visual == FB_VISUAL_TRUECOLOR) { in fb_setcolreg()
661 return -EINVAL; in fb_setcolreg()
663 v = (red << info->var.red.offset) | in fb_setcolreg()
664 (green << info->var.green.offset) | in fb_setcolreg()
665 (blue << info->var.blue.offset); in fb_setcolreg()
667 ((u32 *) (info->pseudo_palette))[regno] = v; in fb_setcolreg()
702 if (par->lcdc_clk_rate != lcdc_clk_rate) { in da8xx_fb_config_clk_divider()
703 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate); in da8xx_fb_config_clk_divider()
705 dev_err(par->dev, in da8xx_fb_config_clk_divider()
710 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); in da8xx_fb_config_clk_divider()
732 *lcdc_clk_rate = par->lcdc_clk_rate; in da8xx_fb_calc_clk_divider()
735 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, in da8xx_fb_calc_clk_divider()
739 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, in da8xx_fb_calc_clk_divider()
753 unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock, in da8xx_fb_calc_config_clk_divider()
776 dev_err(par->dev, "unable to configure clock\n"); in lcd_init()
780 if (panel->sync & FB_SYNC_CLK_INVERT) in lcd_init()
788 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); in lcd_init()
792 /* Configure the vertical and horizontal sync properties. */ in lcd_init()
793 lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len, in lcd_init()
794 panel->lower_margin); in lcd_init()
795 lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len, in lcd_init()
796 panel->right_margin); in lcd_init()
803 bpp = cfg->bpp; in lcd_init()
807 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, in lcd_init()
808 (unsigned int)panel->yres, bpp, in lcd_init()
809 cfg->raster_order); in lcd_init()
815 (cfg->fdd << 12), LCD_RASTER_CTRL_REG); in lcd_init()
850 par->which_dma_channel_done = 0; in lcdc_irq_handler_rev02()
851 lcdc_write(par->dma_start, in lcdc_irq_handler_rev02()
853 lcdc_write(par->dma_end, in lcdc_irq_handler_rev02()
855 par->vsync_flag = 1; in lcdc_irq_handler_rev02()
856 wake_up_interruptible(&par->vsync_wait); in lcdc_irq_handler_rev02()
860 par->which_dma_channel_done = 1; in lcdc_irq_handler_rev02()
861 lcdc_write(par->dma_start, in lcdc_irq_handler_rev02()
863 lcdc_write(par->dma_end, in lcdc_irq_handler_rev02()
865 par->vsync_flag = 1; in lcdc_irq_handler_rev02()
866 wake_up_interruptible(&par->vsync_wait); in lcdc_irq_handler_rev02()
870 * active frame in lcdc_irq_handler_rev02()
915 par->which_dma_channel_done = 0; in lcdc_irq_handler_rev01()
916 lcdc_write(par->dma_start, in lcdc_irq_handler_rev01()
918 lcdc_write(par->dma_end, in lcdc_irq_handler_rev01()
920 par->vsync_flag = 1; in lcdc_irq_handler_rev01()
921 wake_up_interruptible(&par->vsync_wait); in lcdc_irq_handler_rev01()
925 par->which_dma_channel_done = 1; in lcdc_irq_handler_rev01()
926 lcdc_write(par->dma_start, in lcdc_irq_handler_rev01()
928 lcdc_write(par->dma_end, in lcdc_irq_handler_rev01()
930 par->vsync_flag = 1; in lcdc_irq_handler_rev01()
931 wake_up_interruptible(&par->vsync_wait); in lcdc_irq_handler_rev01()
942 struct da8xx_fb_par *par = info->par; in fb_check_var()
943 int bpp = var->bits_per_pixel >> 3; in fb_check_var()
944 unsigned long line_size = var->xres_virtual * bpp; in fb_check_var()
946 if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) in fb_check_var()
947 return -EINVAL; in fb_check_var()
949 switch (var->bits_per_pixel) { in fb_check_var()
952 var->red.offset = 0; in fb_check_var()
953 var->red.length = 8; in fb_check_var()
954 var->green.offset = 0; in fb_check_var()
955 var->green.length = 8; in fb_check_var()
956 var->blue.offset = 0; in fb_check_var()
957 var->blue.length = 8; in fb_check_var()
958 var->transp.offset = 0; in fb_check_var()
959 var->transp.length = 0; in fb_check_var()
960 var->nonstd = 0; in fb_check_var()
963 var->red.offset = 0; in fb_check_var()
964 var->red.length = 4; in fb_check_var()
965 var->green.offset = 0; in fb_check_var()
966 var->green.length = 4; in fb_check_var()
967 var->blue.offset = 0; in fb_check_var()
968 var->blue.length = 4; in fb_check_var()
969 var->transp.offset = 0; in fb_check_var()
970 var->transp.length = 0; in fb_check_var()
971 var->nonstd = FB_NONSTD_REV_PIX_IN_B; in fb_check_var()
974 var->red.offset = 11; in fb_check_var()
975 var->red.length = 5; in fb_check_var()
976 var->green.offset = 5; in fb_check_var()
977 var->green.length = 6; in fb_check_var()
978 var->blue.offset = 0; in fb_check_var()
979 var->blue.length = 5; in fb_check_var()
980 var->transp.offset = 0; in fb_check_var()
981 var->transp.length = 0; in fb_check_var()
982 var->nonstd = 0; in fb_check_var()
985 var->red.offset = 16; in fb_check_var()
986 var->red.length = 8; in fb_check_var()
987 var->green.offset = 8; in fb_check_var()
988 var->green.length = 8; in fb_check_var()
989 var->blue.offset = 0; in fb_check_var()
990 var->blue.length = 8; in fb_check_var()
991 var->nonstd = 0; in fb_check_var()
994 var->transp.offset = 24; in fb_check_var()
995 var->transp.length = 8; in fb_check_var()
996 var->red.offset = 16; in fb_check_var()
997 var->red.length = 8; in fb_check_var()
998 var->green.offset = 8; in fb_check_var()
999 var->green.length = 8; in fb_check_var()
1000 var->blue.offset = 0; in fb_check_var()
1001 var->blue.length = 8; in fb_check_var()
1002 var->nonstd = 0; in fb_check_var()
1005 err = -EINVAL; in fb_check_var()
1008 var->red.msb_right = 0; in fb_check_var()
1009 var->green.msb_right = 0; in fb_check_var()
1010 var->blue.msb_right = 0; in fb_check_var()
1011 var->transp.msb_right = 0; in fb_check_var()
1013 if (line_size * var->yres_virtual > par->vram_size) in fb_check_var()
1014 var->yres_virtual = par->vram_size / line_size; in fb_check_var()
1016 if (var->yres > var->yres_virtual) in fb_check_var()
1017 var->yres = var->yres_virtual; in fb_check_var()
1019 if (var->xres > var->xres_virtual) in fb_check_var()
1020 var->xres = var->xres_virtual; in fb_check_var()
1022 if (var->xres + var->xoffset > var->xres_virtual) in fb_check_var()
1023 var->xoffset = var->xres_virtual - var->xres; in fb_check_var()
1024 if (var->yres + var->yoffset > var->yres_virtual) in fb_check_var()
1025 var->yoffset = var->yres_virtual - var->yres; in fb_check_var()
1027 var->pixclock = da8xx_fb_round_clk(par, var->pixclock); in fb_check_var()
1040 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) { in lcd_da8xx_cpufreq_transition()
1041 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); in lcd_da8xx_cpufreq_transition()
1043 da8xx_fb_calc_config_clk_divider(par, &par->mode); in lcd_da8xx_cpufreq_transition()
1044 if (par->blank == FB_BLANK_UNBLANK) in lcd_da8xx_cpufreq_transition()
1054 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; in lcd_da8xx_cpufreq_register()
1056 return cpufreq_register_notifier(&par->freq_transition, in lcd_da8xx_cpufreq_register()
1062 cpufreq_unregister_notifier(&par->freq_transition, in lcd_da8xx_cpufreq_deregister()
1070 struct da8xx_fb_par *par = info->par; in fb_remove()
1076 if (par->lcd_supply) { in fb_remove()
1077 ret = regulator_disable(par->lcd_supply); in fb_remove()
1079 dev_warn(&dev->dev, "Failed to disable regulator (%pe)\n", in fb_remove()
1090 fb_dealloc_cmap(&info->cmap); in fb_remove()
1091 pm_runtime_put_sync(&dev->dev); in fb_remove()
1092 pm_runtime_disable(&dev->dev); in fb_remove()
1099 * Function to wait for vertical sync which for this LCD peripheral
1104 struct da8xx_fb_par *par = info->par; in fb_wait_for_vsync()
1113 * frame time but there is no way to avoid such a situation. On the in fb_wait_for_vsync()
1119 par->vsync_flag = 0; in fb_wait_for_vsync()
1120 ret = wait_event_interruptible_timeout(par->vsync_wait, in fb_wait_for_vsync()
1121 par->vsync_flag != 0, in fb_wait_for_vsync()
1122 par->vsync_timeout); in fb_wait_for_vsync()
1126 return -ETIMEDOUT; in fb_wait_for_vsync()
1143 return -ENOTTY; in fb_ioctl()
1147 return -EFAULT; in fb_ioctl()
1155 return -EFAULT; in fb_ioctl()
1163 return -EINVAL; in fb_ioctl()
1170 struct da8xx_fb_par *par = info->par; in cfb_blank()
1173 if (par->blank == blank) in cfb_blank()
1176 par->blank = blank; in cfb_blank()
1181 if (par->lcd_supply) { in cfb_blank()
1182 ret = regulator_enable(par->lcd_supply); in cfb_blank()
1191 if (par->lcd_supply) { in cfb_blank()
1192 ret = regulator_disable(par->lcd_supply); in cfb_blank()
1200 ret = -EINVAL; in cfb_blank()
1215 struct da8xx_fb_par *par = fbi->par; in da8xx_pan_display()
1216 struct fb_fix_screeninfo *fix = &fbi->fix; in da8xx_pan_display()
1221 if (var->xoffset != fbi->var.xoffset || in da8xx_pan_display()
1222 var->yoffset != fbi->var.yoffset) { in da8xx_pan_display()
1223 memcpy(&new_var, &fbi->var, sizeof(new_var)); in da8xx_pan_display()
1224 new_var.xoffset = var->xoffset; in da8xx_pan_display()
1225 new_var.yoffset = var->yoffset; in da8xx_pan_display()
1227 ret = -EINVAL; in da8xx_pan_display()
1229 memcpy(&fbi->var, &new_var, sizeof(new_var)); in da8xx_pan_display()
1231 start = fix->smem_start + in da8xx_pan_display()
1232 new_var.yoffset * fix->line_length + in da8xx_pan_display()
1233 new_var.xoffset * fbi->var.bits_per_pixel / 8; in da8xx_pan_display()
1234 end = start + fbi->var.yres * fix->line_length - 1; in da8xx_pan_display()
1235 par->dma_start = start; in da8xx_pan_display()
1236 par->dma_end = end; in da8xx_pan_display()
1237 spin_lock_irqsave(&par->lock_for_chan_update, in da8xx_pan_display()
1239 if (par->which_dma_channel_done == 0) { in da8xx_pan_display()
1240 lcdc_write(par->dma_start, in da8xx_pan_display()
1242 lcdc_write(par->dma_end, in da8xx_pan_display()
1244 } else if (par->which_dma_channel_done == 1) { in da8xx_pan_display()
1245 lcdc_write(par->dma_start, in da8xx_pan_display()
1247 lcdc_write(par->dma_end, in da8xx_pan_display()
1250 spin_unlock_irqrestore(&par->lock_for_chan_update, in da8xx_pan_display()
1260 struct da8xx_fb_par *par = info->par; in da8xxfb_set_par()
1267 fb_var_to_videomode(&par->mode, &info->var); in da8xxfb_set_par()
1269 par->cfg.bpp = info->var.bits_per_pixel; in da8xxfb_set_par()
1271 info->fix.visual = (par->cfg.bpp <= 8) ? in da8xxfb_set_par()
1273 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8; in da8xxfb_set_par()
1275 ret = lcd_init(par, &par->cfg, &par->mode); in da8xxfb_set_par()
1277 dev_err(par->dev, "lcd init failed\n"); in da8xxfb_set_par()
1281 par->dma_start = info->fix.smem_start + in da8xxfb_set_par()
1282 info->var.yoffset * info->fix.line_length + in da8xxfb_set_par()
1283 info->var.xoffset * info->var.bits_per_pixel / 8; in da8xxfb_set_par()
1284 par->dma_end = par->dma_start + in da8xxfb_set_par()
1285 info->var.yres * info->fix.line_length - 1; in da8xxfb_set_par()
1287 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); in da8xxfb_set_par()
1288 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); in da8xxfb_set_par()
1289 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); in da8xxfb_set_par()
1290 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); in da8xxfb_set_par()
1313 struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev); in da8xx_fb_get_videomode()
1319 if (strcmp(fb_pdata->type, lcdc_info->name) == 0) in da8xx_fb_get_videomode()
1324 dev_err(&dev->dev, "no panel found\n"); in da8xx_fb_get_videomode()
1327 dev_info(&dev->dev, "found %s panel\n", lcdc_info->name); in da8xx_fb_get_videomode()
1335 dev_get_platdata(&device->dev); in fb_probe()
1345 dev_err(&device->dev, "Can not get platform data\n"); in fb_probe()
1346 return -ENOENT; in fb_probe()
1351 return -ENODEV; in fb_probe()
1357 tmp_lcdc_clk = devm_clk_get(&device->dev, "fck"); in fb_probe()
1359 return dev_err_probe(&device->dev, PTR_ERR(tmp_lcdc_clk), in fb_probe()
1362 pm_runtime_enable(&device->dev); in fb_probe()
1363 pm_runtime_get_sync(&device->dev); in fb_probe()
1375 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " in fb_probe()
1382 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; in fb_probe()
1385 ret = -EINVAL; in fb_probe()
1390 &device->dev); in fb_probe()
1392 ret = -ENOMEM; in fb_probe()
1396 par = da8xx_fb_info->par; in fb_probe()
1397 par->dev = &device->dev; in fb_probe()
1398 par->lcdc_clk = tmp_lcdc_clk; in fb_probe()
1399 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); in fb_probe()
1401 par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd"); in fb_probe()
1402 if (IS_ERR(par->lcd_supply)) { in fb_probe()
1403 if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) { in fb_probe()
1404 ret = -EPROBE_DEFER; in fb_probe()
1408 par->lcd_supply = NULL; in fb_probe()
1410 ret = regulator_enable(par->lcd_supply); in fb_probe()
1416 par->cfg = *lcd_cfg; in fb_probe()
1421 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; in fb_probe()
1422 ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); in fb_probe()
1423 par->vram_size = roundup(par->vram_size/8, ulcm); in fb_probe()
1424 par->vram_size = par->vram_size * LCD_NUM_BUFFERS; in fb_probe()
1426 par->vram_virt = dmam_alloc_coherent(par->dev, in fb_probe()
1427 par->vram_size, in fb_probe()
1428 &par->vram_phys, in fb_probe()
1430 if (!par->vram_virt) { in fb_probe()
1431 dev_err(&device->dev, in fb_probe()
1433 ret = -EINVAL; in fb_probe()
1437 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; in fb_probe()
1438 da8xx_fb_fix.smem_start = par->vram_phys; in fb_probe()
1439 da8xx_fb_fix.smem_len = par->vram_size; in fb_probe()
1440 da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; in fb_probe()
1442 par->dma_start = par->vram_phys; in fb_probe()
1443 par->dma_end = par->dma_start + lcdc_info->yres * in fb_probe()
1444 da8xx_fb_fix.line_length - 1; in fb_probe()
1447 par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE, in fb_probe()
1448 &par->p_palette_base, in fb_probe()
1450 if (!par->v_palette_base) { in fb_probe()
1451 dev_err(&device->dev, in fb_probe()
1453 ret = -EINVAL; in fb_probe()
1457 par->irq = platform_get_irq(device, 0); in fb_probe()
1458 if (par->irq < 0) { in fb_probe()
1459 ret = -ENOENT; in fb_probe()
1464 lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; in fb_probe()
1465 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; in fb_probe()
1468 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; in fb_probe()
1469 da8xx_fb_info->fix = da8xx_fb_fix; in fb_probe()
1470 da8xx_fb_info->var = da8xx_fb_var; in fb_probe()
1471 da8xx_fb_info->fbops = &da8xx_fb_ops; in fb_probe()
1472 da8xx_fb_info->pseudo_palette = par->pseudo_palette; in fb_probe()
1473 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? in fb_probe()
1476 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); in fb_probe()
1479 da8xx_fb_info->cmap.len = par->palette_sz; in fb_probe()
1488 init_waitqueue_head(&par->vsync_wait); in fb_probe()
1489 par->vsync_timeout = HZ / 5; in fb_probe()
1490 par->which_dma_channel_done = -1; in fb_probe()
1491 spin_lock_init(&par->lock_for_chan_update); in fb_probe()
1495 dev_err(&device->dev, in fb_probe()
1497 ret = -EINVAL; in fb_probe()
1504 dev_err(&device->dev, "failed to register cpufreq\n"); in fb_probe()
1516 ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0, in fb_probe()
1530 fb_dealloc_cmap(&da8xx_fb_info->cmap); in fb_probe()
1536 pm_runtime_put_sync(&device->dev); in fb_probe()
1537 pm_runtime_disable(&device->dev); in fb_probe()
1609 struct da8xx_fb_par *par = info->par; in fb_suspend()
1613 if (par->lcd_supply) { in fb_suspend()
1614 ret = regulator_disable(par->lcd_supply); in fb_suspend()
1630 struct da8xx_fb_par *par = info->par; in fb_resume()
1636 if (par->blank == FB_BLANK_UNBLANK) { in fb_resume()
1639 if (par->lcd_supply) { in fb_resume()
1640 ret = regulator_enable(par->lcd_supply); in fb_resume()
1665 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");