1 // SPDX-License-Identifier: GPL-2.0-only
58 #define CG3_CR_ENABLE_INTS      0x80
59 #define CG3_CR_ENABLE_VIDEO     0x40
60 #define CG3_CR_ENABLE_TIMING    0x20
61 #define CG3_CR_ENABLE_CURCMP    0x10
62 #define CG3_CR_XTAL_MASK        0x0c
63 #define CG3_CR_DIVISOR_MASK     0x03
66 #define CG3_SR_PENDING_INT      0x80
67 #define CG3_SR_RES_MASK         0x70
68 #define CG3_SR_1152_900_76_A    0x40
69 #define CG3_SR_1152_900_76_B    0x60
70 #define CG3_SR_ID_MASK          0x0f
71 #define CG3_SR_ID_COLOR         0x01
72 #define CG3_SR_ID_MONO          0x02
73 #define CG3_SR_ID_MONO_ECL      0x03
76 	CG3_AT_66HZ = 0,
109 #define CG3_REGS_OFFSET	     0x400000UL
110 #define CG3_RAM_OFFSET	     0x800000UL
118 #define CG3_FLAG_BLANKED	0x00000001
119 #define CG3_FLAG_RDI		0x00000002
125  *      cg3_setcolreg - Optional function. Sets a color register.
126  *      @regno: boolean, 0 copy local, 1 get_user() function
142 	struct cg3_par *par = (struct cg3_par *) info->par;  in cg3_setcolreg()
143 	struct bt_regs __iomem *bt = &par->regs->cmap;  in cg3_setcolreg()
156 	spin_lock_irqsave(&par->lock, flags);  in cg3_setcolreg()
158 	p8 = (u8 *)par->sw_cmap + (regno * 3);  in cg3_setcolreg()
159 	p8[0] = red;  in cg3_setcolreg()
164 #define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */  in cg3_setcolreg()
167 	p32 = &par->sw_cmap[D4M3(regno)];  in cg3_setcolreg()
168 	sbus_writel(D4M4(regno), &bt->addr);  in cg3_setcolreg()
169 	while (count--)  in cg3_setcolreg()
170 		sbus_writel(*p32++, &bt->color_map);  in cg3_setcolreg()
175 	spin_unlock_irqrestore(&par->lock, flags);  in cg3_setcolreg()
177 	return 0;  in cg3_setcolreg()
181  *      cg3_blank - Optional function.  Blanks the display.
187 	struct cg3_par *par = (struct cg3_par *) info->par;  in cg3_blank()
188 	struct cg3_regs __iomem *regs = par->regs;  in cg3_blank()
192 	spin_lock_irqsave(&par->lock, flags);  in cg3_blank()
196 		val = sbus_readb(&regs->control);  in cg3_blank()
198 		sbus_writeb(val, &regs->control);  in cg3_blank()
199 		par->flags &= ~CG3_FLAG_BLANKED;  in cg3_blank()
206 		val = sbus_readb(&regs->control);  in cg3_blank()
208 		sbus_writeb(val, &regs->control);  in cg3_blank()
209 		par->flags |= CG3_FLAG_BLANKED;  in cg3_blank()
213 	spin_unlock_irqrestore(&par->lock, flags);  in cg3_blank()
215 	return 0;  in cg3_blank()
224 	{ .size = 0 }
229 	struct cg3_par *par = (struct cg3_par *)info->par;  in cg3_mmap()
232 				  info->fix.smem_start, info->fix.smem_len,  in cg3_mmap()
233 				  par->which_io,  in cg3_mmap()
240 				   FBTYPE_SUN3COLOR, 8, info->fix.smem_len);  in cg3_ioctl()
250 	snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);  in cg3_init_fix()
252 	info->fix.type = FB_TYPE_PACKED_PIXELS;  in cg3_init_fix()
253 	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;  in cg3_init_fix()
255 	info->fix.line_length = linebytes;  in cg3_init_fix()
257 	info->fix.accel = FB_ACCEL_SUN_CGTHREE;  in cg3_init_fix()
272 			if (hh && *p == '-') {  in cg3_rdi_maybe_fixup_var()
273 				if (var->xres != ww ||  in cg3_rdi_maybe_fixup_var()
274 				    var->yres != hh) {  in cg3_rdi_maybe_fixup_var()
275 					var->xres = var->xres_virtual = ww;  in cg3_rdi_maybe_fixup_var()
276 					var->yres = var->yres_virtual = hh;  in cg3_rdi_maybe_fixup_var()
283 static u8 cg3regvals_66hz[] = {	/* 1152 x 900, 66 Hz */
284 	0x14, 0xbb,	0x15, 0x2b,	0x16, 0x04,	0x17, 0x14,
285 	0x18, 0xae,	0x19, 0x03,	0x1a, 0xa8,	0x1b, 0x24,
286 	0x1c, 0x01,	0x1d, 0x05,	0x1e, 0xff,	0x1f, 0x01,
287 	0x10, 0x20,	0
290 static u8 cg3regvals_76hz[] = {	/* 1152 x 900, 76 Hz */
291 	0x14, 0xb7,	0x15, 0x27,	0x16, 0x03,	0x17, 0x0f,
292 	0x18, 0xae,	0x19, 0x03,	0x1a, 0xae,	0x1b, 0x2a,
293 	0x1c, 0x01,	0x1d, 0x09,	0x1e, 0xff,	0x1f, 0x01,
294 	0x10, 0x24,	0
298 	0x14, 0x70,	0x15, 0x20,	0x16, 0x08,	0x17, 0x10,
299 	0x18, 0x06,	0x19, 0x02,	0x1a, 0x31,	0x1b, 0x51,
300 	0x1c, 0x06,	0x1d, 0x0c,	0x1e, 0xff,	0x1f, 0x01,
301 	0x10, 0x22,	0
309 	4, 0xff,	5, 0x00,	6, 0x70,	7, 0x00,	0
317 	if (par->flags & CG3_FLAG_RDI)  in cg3_do_default_mode()
320 		u8 status = sbus_readb(&par->regs->status), mon;  in cg3_do_default_mode()
331 			return -EINVAL;  in cg3_do_default_mode()
336 		u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];  in cg3_do_default_mode()
342 		regp = (u8 __iomem *)&par->regs->cmap.addr;  in cg3_do_default_mode()
343 		sbus_writeb(p[0], regp);  in cg3_do_default_mode()
344 		regp = (u8 __iomem *)&par->regs->cmap.control;  in cg3_do_default_mode()
347 	return 0;  in cg3_do_default_mode()
352 	struct device_node *dp = op->dev.of_node;  in cg3_probe()
357 	info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);  in cg3_probe()
359 	err = -ENOMEM;  in cg3_probe()
362 	par = info->par;  in cg3_probe()
364 	spin_lock_init(&par->lock);  in cg3_probe()
366 	info->fix.smem_start = op->resource[0].start;  in cg3_probe()
367 	par->which_io = op->resource[0].flags & IORESOURCE_BITS;  in cg3_probe()
369 	sbusfb_fill_var(&info->var, dp, 8);  in cg3_probe()
370 	info->var.red.length = 8;  in cg3_probe()
371 	info->var.green.length = 8;  in cg3_probe()
372 	info->var.blue.length = 8;  in cg3_probe()
374 		par->flags |= CG3_FLAG_RDI;  in cg3_probe()
375 	if (par->flags & CG3_FLAG_RDI)  in cg3_probe()
376 		cg3_rdi_maybe_fixup_var(&info->var, dp);  in cg3_probe()
379 					  info->var.xres);  in cg3_probe()
380 	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);  in cg3_probe()
382 	par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,  in cg3_probe()
384 	if (!par->regs)  in cg3_probe()
387 	info->flags = FBINFO_DEFAULT;  in cg3_probe()
388 	info->fbops = &cg3_ops;  in cg3_probe()
389 	info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,  in cg3_probe()
390 				       info->fix.smem_len, "cg3 ram");  in cg3_probe()
391 	if (!info->screen_base)  in cg3_probe()
402 	err = fb_alloc_cmap(&info->cmap, 256, 0);  in cg3_probe()
406 	fb_set_cmap(&info->cmap, info);  in cg3_probe()
411 	if (err < 0)  in cg3_probe()
414 	dev_set_drvdata(&op->dev, info);  in cg3_probe()
417 	       dp, par->which_io, info->fix.smem_start);  in cg3_probe()
419 	return 0;  in cg3_probe()
422 	fb_dealloc_cmap(&info->cmap);  in cg3_probe()
425 	of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);  in cg3_probe()
428 	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));  in cg3_probe()
439 	struct fb_info *info = dev_get_drvdata(&op->dev);  in cg3_remove()
440 	struct cg3_par *par = info->par;  in cg3_remove()
443 	fb_dealloc_cmap(&info->cmap);  in cg3_remove()
445 	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));  in cg3_remove()
446 	of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);  in cg3_remove()
450 	return 0;  in cg3_remove()
476 		return -ENODEV;  in cg3_init()