Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
9 * - Code cleanup
12 * - 15/16 bit cleanup
13 * - fix panning
16 * - pmac-specific PM stuff
17 * - various fixes & cleanups
20 * - FB_ACTIVATE fixes
23 * - Convert to new framebuffer API,
27 * - PCI hotplug
30 * - PCI ID update
31 * - replace ROM BIOS search
36 * - monitor sensing (DDC)
37 * - virtual display
38 * - other platform support (only ppc/x86 supported)
39 * - hardware cursor support
46 * example code and hardware. Thanks Nitya. -atong and brad
98 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
99 640, 480, 640, 480, 0, 0, 8, 0,
100 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
101 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
102 0, FB_VMODE_NONINTERLACED
106 /* default to 1024x768 at 75Hz on PPC - this will work
109 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
110 1024, 768, 1024, 768, 0, 0, 8, 0,
111 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
112 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
119 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
131 .sync = 0,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
277 { 0, }
345 .name = "128-bit SDR SGRAM (1:1)",
359 .name = "64-bit SDR SGRAM (2:1)",
373 .name = "64-bit DDR SGRAM",
382 .mmio_len = 0x2000,
393 static int default_crt_on = 0;
521 * - endian conversions may possibly be avoided by
527 return readl (par->regbase + regindex); in _aty_ld_le32()
533 writel (val, par->regbase + regindex); in _aty_st_le32()
539 return readb (par->regbase + regindex); in _aty_ld_8()
545 writeb (val, par->regbase + regindex); in _aty_st_8()
564 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); in _aty_ld_pll()
572 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
591 reset = 0; in aty_pll_wait_readupdate()
614 int flag = 0; in register_test()
618 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); in register_test()
619 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { in register_test()
620 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); in register_test()
622 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) in register_test()
639 for (i = 0; i < 2000000; i++) { in do_wait_for_fifo()
640 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; in do_wait_for_fifo()
641 if (par->fifo_slots >= entries) in do_wait_for_fifo()
656 for (i = 0; i < 2000000; i++) { in wait_for_idle()
659 par->blitter_may_be_busy = 0; in wait_for_idle()
670 if (par->fifo_slots < entries) in wait_for_fifo()
672 par->fifo_slots -= entries; in wait_for_fifo()
682 tmp &= ~(0x00ff); in aty128_flush_pixel_cache()
683 tmp |= 0x00ff; in aty128_flush_pixel_cache()
686 for (i = 0; i < 2000000; i++) in aty128_flush_pixel_cache()
701 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); in aty128_reset_engine()
728 aty_st_le32(SCALE_3D_CNTL, 0x00000000); in aty128_init_engine()
732 pitch_value = par->crtc.pitch; in aty128_init_engine()
733 if (par->crtc.bpp == 24) { in aty128_init_engine()
739 aty_st_le32(DEFAULT_OFFSET, 0x00000000); in aty128_init_engine()
745 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); in aty128_init_engine()
754 (depth_to_dst(par->crtc.depth) << 8) | in aty128_init_engine()
767 aty_st_le32(DST_BRES_ERR, 0); in aty128_init_engine()
768 aty_st_le32(DST_BRES_INC, 0); in aty128_init_engine()
769 aty_st_le32(DST_BRES_DEC, 0); in aty128_init_engine()
772 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
773 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
776 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
777 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
780 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); in aty128_init_engine()
801 return -EINVAL; in depth_to_dst()
821 temp &= 0x00ffffffu; in aty128_map_ROM()
822 temp |= 0x04 << 24; in aty128_map_ROM()
834 if (BIOS_IN16(0) != 0xaa55) { in aty128_map_ROM()
836 " be 0xaa55\n", BIOS_IN16(0)); in aty128_map_ROM()
841 dptr = BIOS_IN16(0x18); in aty128_map_ROM()
850 * dual-image ATI card. in aty128_map_ROM()
853 * u32 signature; + 0x00 in aty128_map_ROM()
854 * u16 vendor; + 0x04 in aty128_map_ROM()
855 * u16 device; + 0x06 in aty128_map_ROM()
856 * u16 reserved_1; + 0x08 in aty128_map_ROM()
857 * u16 dlen; + 0x0a in aty128_map_ROM()
858 * u8 drevision; + 0x0c in aty128_map_ROM()
859 * u8 class_hi; + 0x0d in aty128_map_ROM()
860 * u16 class_lo; + 0x0e in aty128_map_ROM()
861 * u16 ilen; + 0x10 in aty128_map_ROM()
862 * u16 irevision; + 0x12 in aty128_map_ROM()
863 * u8 type; + 0x14 in aty128_map_ROM()
864 * u8 indicator; + 0x15 in aty128_map_ROM()
865 * u16 reserved_2; + 0x16 in aty128_map_ROM()
873 rom_type = BIOS_IN8(dptr + 0x14); in aty128_map_ROM()
875 case 0: in aty128_map_ROM()
882 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); in aty128_map_ROM()
903 bios_hdr = BIOS_IN16(0x48); in aty128_get_pllinfo()
904 bios_pll = BIOS_IN16(bios_hdr + 0x30); in aty128_get_pllinfo()
906 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); in aty128_get_pllinfo()
907 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); in aty128_get_pllinfo()
908 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); in aty128_get_pllinfo()
909 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); in aty128_get_pllinfo()
910 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); in aty128_get_pllinfo()
913 par->constants.ppll_max, par->constants.ppll_min, in aty128_get_pllinfo()
914 par->constants.xclk, par->constants.ref_divider, in aty128_get_pllinfo()
915 par->constants.ref_clk); in aty128_get_pllinfo()
930 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { in aty128_find_mem_vbios()
931 rom_base = ioremap(segstart, 0x10000); in aty128_find_mem_vbios()
934 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) in aty128_find_mem_vbios()
955 static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; in aty128_timings()
958 if (!par->constants.ref_clk) in aty128_timings()
959 par->constants.ref_clk = 2950; in aty128_timings()
963 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; in aty128_timings()
964 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; in aty128_timings()
965 M = x_mpll_ref_fb_div & 0x0000ff; in aty128_timings()
967 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), in aty128_timings()
970 par->constants.ref_divider = in aty128_timings()
974 if (!par->constants.ref_divider) { in aty128_timings()
975 par->constants.ref_divider = 0x3b; in aty128_timings()
977 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); in aty128_timings()
980 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); in aty128_timings()
984 if (!par->constants.ppll_min) in aty128_timings()
985 par->constants.ppll_min = 12500; in aty128_timings()
986 if (!par->constants.ppll_max) in aty128_timings()
987 par->constants.ppll_max = 25000; /* 23000 on some cards? */ in aty128_timings()
988 if (!par->constants.xclk) in aty128_timings()
989 par->constants.xclk = 0x1d4d; /* same as mclk */ in aty128_timings()
991 par->constants.fifo_width = 128; in aty128_timings()
992 par->constants.fifo_depth = 32; in aty128_timings()
994 switch (aty_ld_le32(MEM_CNTL) & 0x3) { in aty128_timings()
995 case 0: in aty128_timings()
996 par->mem = &sdr_128; in aty128_timings()
999 par->mem = &sdr_sgram; in aty128_timings()
1002 par->mem = &ddr_sgram; in aty128_timings()
1005 par->mem = &sdr_sgram; in aty128_timings()
1019 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); in aty128_set_crtc()
1020 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); in aty128_set_crtc()
1021 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); in aty128_set_crtc()
1022 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
1023 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); in aty128_set_crtc()
1024 aty_st_le32(CRTC_PITCH, crtc->pitch); in aty128_set_crtc()
1025 aty_st_le32(CRTC_OFFSET, crtc->offset); in aty128_set_crtc()
1026 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); in aty128_set_crtc()
1028 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); in aty128_set_crtc()
1041 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; in aty128_var_to_crtc()
1044 xres = var->xres; in aty128_var_to_crtc()
1045 yres = var->yres; in aty128_var_to_crtc()
1046 vxres = var->xres_virtual; in aty128_var_to_crtc()
1047 vyres = var->yres_virtual; in aty128_var_to_crtc()
1048 xoffset = var->xoffset; in aty128_var_to_crtc()
1049 yoffset = var->yoffset; in aty128_var_to_crtc()
1050 bpp = var->bits_per_pixel; in aty128_var_to_crtc()
1051 left = var->left_margin; in aty128_var_to_crtc()
1052 right = var->right_margin; in aty128_var_to_crtc()
1053 upper = var->upper_margin; in aty128_var_to_crtc()
1054 lower = var->lower_margin; in aty128_var_to_crtc()
1055 hslen = var->hsync_len; in aty128_var_to_crtc()
1056 vslen = var->vsync_len; in aty128_var_to_crtc()
1057 sync = var->sync; in aty128_var_to_crtc()
1058 vmode = var->vmode; in aty128_var_to_crtc()
1063 depth = (var->green.length == 6) ? 16 : 15; in aty128_var_to_crtc()
1068 return -EINVAL; in aty128_var_to_crtc()
1083 if (dst == -EINVAL) { in aty128_var_to_crtc()
1085 return -EINVAL; in aty128_var_to_crtc()
1092 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { in aty128_var_to_crtc()
1094 return -EINVAL; in aty128_var_to_crtc()
1097 h_disp = (xres >> 3) - 1; in aty128_var_to_crtc()
1098 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; in aty128_var_to_crtc()
1100 v_disp = yres - 1; in aty128_var_to_crtc()
1101 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; in aty128_var_to_crtc()
1104 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { in aty128_var_to_crtc()
1106 return -EINVAL; in aty128_var_to_crtc()
1110 if (h_sync_wid == 0) in aty128_var_to_crtc()
1112 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ in aty128_var_to_crtc()
1113 h_sync_wid = 0x3f; in aty128_var_to_crtc()
1118 if (v_sync_wid == 0) in aty128_var_to_crtc()
1120 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ in aty128_var_to_crtc()
1121 v_sync_wid = 0x1f; in aty128_var_to_crtc()
1125 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; in aty128_var_to_crtc()
1126 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; in aty128_var_to_crtc()
1128 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; in aty128_var_to_crtc()
1130 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); in aty128_var_to_crtc()
1132 crtc->h_total = h_total | (h_disp << 16); in aty128_var_to_crtc()
1133 crtc->v_total = v_total | (v_disp << 16); in aty128_var_to_crtc()
1135 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | in aty128_var_to_crtc()
1137 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | in aty128_var_to_crtc()
1140 crtc->pitch = vxres >> 3; in aty128_var_to_crtc()
1142 crtc->offset = 0; in aty128_var_to_crtc()
1144 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) in aty128_var_to_crtc()
1145 crtc->offset_cntl = 0x00010000; in aty128_var_to_crtc()
1147 crtc->offset_cntl = 0; in aty128_var_to_crtc()
1149 crtc->vxres = vxres; in aty128_var_to_crtc()
1150 crtc->vyres = vyres; in aty128_var_to_crtc()
1151 crtc->xoffset = xoffset; in aty128_var_to_crtc()
1152 crtc->yoffset = yoffset; in aty128_var_to_crtc()
1153 crtc->depth = depth; in aty128_var_to_crtc()
1154 crtc->bpp = bpp; in aty128_var_to_crtc()
1156 return 0; in aty128_var_to_crtc()
1164 var->red.msb_right = 0; in aty128_pix_width_to_var()
1165 var->green.msb_right = 0; in aty128_pix_width_to_var()
1166 var->blue.offset = 0; in aty128_pix_width_to_var()
1167 var->blue.msb_right = 0; in aty128_pix_width_to_var()
1168 var->transp.offset = 0; in aty128_pix_width_to_var()
1169 var->transp.length = 0; in aty128_pix_width_to_var()
1170 var->transp.msb_right = 0; in aty128_pix_width_to_var()
1173 var->bits_per_pixel = 8; in aty128_pix_width_to_var()
1174 var->red.offset = 0; in aty128_pix_width_to_var()
1175 var->red.length = 8; in aty128_pix_width_to_var()
1176 var->green.offset = 0; in aty128_pix_width_to_var()
1177 var->green.length = 8; in aty128_pix_width_to_var()
1178 var->blue.length = 8; in aty128_pix_width_to_var()
1181 var->bits_per_pixel = 16; in aty128_pix_width_to_var()
1182 var->red.offset = 10; in aty128_pix_width_to_var()
1183 var->red.length = 5; in aty128_pix_width_to_var()
1184 var->green.offset = 5; in aty128_pix_width_to_var()
1185 var->green.length = 5; in aty128_pix_width_to_var()
1186 var->blue.length = 5; in aty128_pix_width_to_var()
1189 var->bits_per_pixel = 16; in aty128_pix_width_to_var()
1190 var->red.offset = 11; in aty128_pix_width_to_var()
1191 var->red.length = 5; in aty128_pix_width_to_var()
1192 var->green.offset = 5; in aty128_pix_width_to_var()
1193 var->green.length = 6; in aty128_pix_width_to_var()
1194 var->blue.length = 5; in aty128_pix_width_to_var()
1197 var->bits_per_pixel = 24; in aty128_pix_width_to_var()
1198 var->red.offset = 16; in aty128_pix_width_to_var()
1199 var->red.length = 8; in aty128_pix_width_to_var()
1200 var->green.offset = 8; in aty128_pix_width_to_var()
1201 var->green.length = 8; in aty128_pix_width_to_var()
1202 var->blue.length = 8; in aty128_pix_width_to_var()
1205 var->bits_per_pixel = 32; in aty128_pix_width_to_var()
1206 var->red.offset = 16; in aty128_pix_width_to_var()
1207 var->red.length = 8; in aty128_pix_width_to_var()
1208 var->green.offset = 8; in aty128_pix_width_to_var()
1209 var->green.length = 8; in aty128_pix_width_to_var()
1210 var->blue.length = 8; in aty128_pix_width_to_var()
1211 var->transp.offset = 24; in aty128_pix_width_to_var()
1212 var->transp.length = 8; in aty128_pix_width_to_var()
1216 return -EINVAL; in aty128_pix_width_to_var()
1219 return 0; in aty128_pix_width_to_var()
1232 h_total = crtc->h_total & 0x1ff; in aty128_crtc_to_var()
1233 h_disp = (crtc->h_total >> 16) & 0xff; in aty128_crtc_to_var()
1234 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; in aty128_crtc_to_var()
1235 h_sync_dly = crtc->h_sync_strt_wid & 0x7; in aty128_crtc_to_var()
1236 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; in aty128_crtc_to_var()
1237 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; in aty128_crtc_to_var()
1238 v_total = crtc->v_total & 0x7ff; in aty128_crtc_to_var()
1239 v_disp = (crtc->v_total >> 16) & 0x7ff; in aty128_crtc_to_var()
1240 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; in aty128_crtc_to_var()
1241 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; in aty128_crtc_to_var()
1242 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; in aty128_crtc_to_var()
1243 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; in aty128_crtc_to_var()
1244 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; in aty128_crtc_to_var()
1249 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; in aty128_crtc_to_var()
1250 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; in aty128_crtc_to_var()
1252 upper = v_total - v_sync_strt - v_sync_wid; in aty128_crtc_to_var()
1253 lower = v_sync_strt - v_disp; in aty128_crtc_to_var()
1255 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | in aty128_crtc_to_var()
1256 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | in aty128_crtc_to_var()
1257 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); in aty128_crtc_to_var()
1261 var->xres = xres; in aty128_crtc_to_var()
1262 var->yres = yres; in aty128_crtc_to_var()
1263 var->xres_virtual = crtc->vxres; in aty128_crtc_to_var()
1264 var->yres_virtual = crtc->vyres; in aty128_crtc_to_var()
1265 var->xoffset = crtc->xoffset; in aty128_crtc_to_var()
1266 var->yoffset = crtc->yoffset; in aty128_crtc_to_var()
1267 var->left_margin = left; in aty128_crtc_to_var()
1268 var->right_margin = right; in aty128_crtc_to_var()
1269 var->upper_margin = upper; in aty128_crtc_to_var()
1270 var->lower_margin = lower; in aty128_crtc_to_var()
1271 var->hsync_len = hslen; in aty128_crtc_to_var()
1272 var->vsync_len = vslen; in aty128_crtc_to_var()
1273 var->sync = sync; in aty128_crtc_to_var()
1274 var->vmode = FB_VMODE_NONINTERLACED; in aty128_crtc_to_var()
1276 return 0; in aty128_crtc_to_var()
1295 struct fb_info *info = pci_get_drvdata(par->pdev); in aty128_set_lcd_enable()
1326 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 in aty128_set_pll()
1338 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()
1343 div3 |= pll->feedback_divider; in aty128_set_pll()
1345 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1353 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ in aty128_set_pll()
1364 const struct aty128_constants c = par->constants; in aty128_var_to_pll()
1368 int i = 0; in aty128_var_to_pll()
1380 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { in aty128_var_to_pll()
1383 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1389 return -EINVAL; in aty128_var_to_pll()
1395 pll->feedback_divider = round_div(n, d); in aty128_var_to_pll()
1396 pll->vclk = vclk; in aty128_var_to_pll()
1399 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
1400 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
1403 return 0; in aty128_var_to_pll()
1410 var->pixclock = 100000000 / pll->vclk; in aty128_pll_to_var()
1412 return 0; in aty128_pll_to_var()
1419 aty_st_le32(DDA_CONFIG, dsp->dda_config); in aty128_set_fifo()
1420 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); in aty128_set_fifo()
1429 const struct aty128_meminfo *m = par->mem; in aty128_ddafifo()
1430 u32 xclk = par->constants.xclk; in aty128_ddafifo()
1431 u32 fifo_width = par->constants.fifo_width; in aty128_ddafifo()
1432 u32 fifo_depth = par->constants.fifo_depth; in aty128_ddafifo()
1440 d = pll->vclk * bpp; in aty128_ddafifo()
1443 ron = 4 * m->MB + in aty128_ddafifo()
1444 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + in aty128_ddafifo()
1445 2 * m->Trp + in aty128_ddafifo()
1446 m->Twr + in aty128_ddafifo()
1447 m->CL + in aty128_ddafifo()
1448 m->Tr2w + in aty128_ddafifo()
1453 b = 0; in aty128_ddafifo()
1460 ron <<= (11 - p); in aty128_ddafifo()
1462 n <<= (11 - p); in aty128_ddafifo()
1464 roff = x * (fifo_depth - 4); in aty128_ddafifo()
1466 if ((ron + m->Rloop) >= roff) { in aty128_ddafifo()
1468 return -EINVAL; in aty128_ddafifo()
1472 p, m->Rloop, x, ron, roff); in aty128_ddafifo()
1474 dsp->dda_config = p << 16 | m->Rloop << 20 | x; in aty128_ddafifo()
1475 dsp->dda_on_off = ron << 16 | roff; in aty128_ddafifo()
1477 return 0; in aty128_ddafifo()
1486 struct aty128fb_par *par = info->par; in aty128fb_set_par()
1490 if ((err = aty128_decode_var(&info->var, par)) != 0) in aty128fb_set_par()
1493 if (par->blitter_may_be_busy) in aty128fb_set_par()
1497 aty_st_le32(OVR_CLR, 0); in aty128fb_set_par()
1498 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); in aty128fb_set_par()
1499 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); in aty128fb_set_par()
1500 aty_st_le32(OV0_SCALE_CNTL, 0); in aty128fb_set_par()
1501 aty_st_le32(MPP_TB_CONFIG, 0); in aty128fb_set_par()
1502 aty_st_le32(MPP_GP_CONFIG, 0); in aty128fb_set_par()
1503 aty_st_le32(SUBPIC_CNTL, 0); in aty128fb_set_par()
1504 aty_st_le32(VIPH_CONTROL, 0); in aty128fb_set_par()
1505 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ in aty128fb_set_par()
1506 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ in aty128fb_set_par()
1507 aty_st_le32(CAP0_TRIG_CNTL, 0); in aty128fb_set_par()
1508 aty_st_le32(CAP1_TRIG_CNTL, 0); in aty128fb_set_par()
1512 aty128_set_crtc(&par->crtc, par); in aty128fb_set_par()
1513 aty128_set_pll(&par->pll, par); in aty128fb_set_par()
1514 aty128_set_fifo(&par->fifo_reg, par); in aty128fb_set_par()
1519 if (par->crtc.bpp == 32) in aty128fb_set_par()
1521 else if (par->crtc.bpp == 16) in aty128fb_set_par()
1526 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ in aty128fb_set_par()
1528 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; in aty128fb_set_par()
1529 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR in aty128fb_set_par()
1532 if (par->chip_gen == rage_M3) { in aty128fb_set_par()
1533 aty128_set_crt_enable(par, par->crt_on); in aty128fb_set_par()
1534 aty128_set_lcd_enable(par, par->lcd_on); in aty128fb_set_par()
1536 if (par->accel_flags & FB_ACCELF_TEXT) in aty128fb_set_par()
1540 btext_update_display(info->fix.smem_start, in aty128fb_set_par()
1541 (((par->crtc.h_total>>16) & 0xff)+1)*8, in aty128fb_set_par()
1542 ((par->crtc.v_total>>16) & 0x7ff)+1, in aty128fb_set_par()
1543 par->crtc.bpp, in aty128fb_set_par()
1544 par->crtc.vxres*par->crtc.bpp/8); in aty128fb_set_par()
1547 return 0; in aty128fb_set_par()
1565 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) in aty128_decode_var()
1571 par->crtc = crtc; in aty128_decode_var()
1572 par->pll = pll; in aty128_decode_var()
1573 par->fifo_reg = fifo_reg; in aty128_decode_var()
1574 par->accel_flags = var->accel_flags; in aty128_decode_var()
1576 return 0; in aty128_decode_var()
1585 if ((err = aty128_crtc_to_var(&par->crtc, var))) in aty128_encode_var()
1588 if ((err = aty128_pll_to_var(&par->pll, var))) in aty128_encode_var()
1591 var->nonstd = 0; in aty128_encode_var()
1592 var->activate = 0; in aty128_encode_var()
1594 var->height = -1; in aty128_encode_var()
1595 var->width = -1; in aty128_encode_var()
1596 var->accel_flags = par->accel_flags; in aty128_encode_var()
1598 return 0; in aty128_encode_var()
1608 par = *(struct aty128fb_par *)info->par; in aty128fb_check_var()
1609 if ((err = aty128_decode_var(var, &par)) != 0) in aty128fb_check_var()
1612 return 0; in aty128fb_check_var()
1622 struct aty128fb_par *par = fb->par; in aty128fb_pan_display()
1627 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; in aty128fb_pan_display()
1628 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; in aty128fb_pan_display()
1630 xoffset = (var->xoffset +7) & ~7; in aty128fb_pan_display()
1631 yoffset = var->yoffset; in aty128fb_pan_display()
1633 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) in aty128fb_pan_display()
1634 return -EINVAL; in aty128fb_pan_display()
1636 par->crtc.xoffset = xoffset; in aty128fb_pan_display()
1637 par->crtc.yoffset = yoffset; in aty128fb_pan_display()
1639 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) in aty128fb_pan_display()
1642 if (par->crtc.bpp == 24) in aty128fb_pan_display()
1647 return 0; in aty128fb_pan_display()
1657 if (par->chip_gen == rage_M3) { in aty128_st_pal()
1668 struct aty128fb_par *par = info->par; in aty128fb_sync()
1670 if (par->blitter_may_be_busy) in aty128fb_sync()
1672 return 0; in aty128fb_sync()
1681 return 0; in aty128fb_setup()
1685 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); in aty128fb_setup()
1688 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); in aty128fb_setup()
1692 backlight = simple_strtoul(this_opt+10, NULL, 0); in aty128fb_setup()
1703 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); in aty128fb_setup()
1704 if (vmode > 0 && vmode <= VMODE_MAX) in aty128fb_setup()
1708 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); in aty128fb_setup()
1710 case 0: in aty128fb_setup()
1728 return 0; in aty128fb_setup()
1734 #define MAX_LEVEL 0xFF
1739 struct fb_info *info = pci_get_drvdata(par->pdev); in aty128_bl_get_level_brightness()
1744 atylevel = MAX_LEVEL - in aty128_bl_get_level_brightness()
1745 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); in aty128_bl_get_level_brightness()
1747 if (atylevel < 0) in aty128_bl_get_level_brightness()
1748 atylevel = 0; in aty128_bl_get_level_brightness()
1769 if (bd->props.power != FB_BLANK_UNBLANK || in aty128_bl_update_status()
1770 bd->props.fb_blank != FB_BLANK_UNBLANK || in aty128_bl_update_status()
1771 !par->lcd_on) in aty128_bl_update_status()
1772 level = 0; in aty128_bl_update_status()
1774 level = bd->props.brightness; in aty128_bl_update_status()
1777 if (level > 0) { in aty128_bl_update_status()
1800 reg |= (aty128_bl_get_level_brightness(par, 0) << in aty128_bl_update_status()
1815 return 0; in aty128_bl_update_status()
1824 if (info->bl_dev) { in aty128_bl_set_power()
1825 info->bl_dev->props.power = power; in aty128_bl_set_power()
1826 backlight_update_status(info->bl_dev); in aty128_bl_set_power()
1833 struct fb_info *info = pci_get_drvdata(par->pdev); in aty128_bl_init()
1838 if (par->chip_gen != rage_M3) in aty128_bl_init()
1846 snprintf(name, sizeof(name), "aty128bl%d", info->node); in aty128_bl_init()
1848 memset(&props, 0, sizeof(struct backlight_properties)); in aty128_bl_init()
1850 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; in aty128_bl_init()
1851 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, in aty128_bl_init()
1854 info->bl_dev = NULL; in aty128_bl_init()
1859 info->bl_dev = bd; in aty128_bl_init()
1860 fb_bl_default_curve(info, 0, in aty128_bl_init()
1864 bd->props.brightness = bd->props.max_brightness; in aty128_bl_init()
1865 bd->props.power = FB_BLANK_UNBLANK; in aty128_bl_init()
1894 pci_restore_state(par->pdev); in aty128_early_resume()
1895 aty128_do_resume(par->pdev); in aty128_early_resume()
1903 struct aty128fb_par *par = info->par; in aty128_init()
1910 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; in aty128_init()
1913 video_card[8] = ent->device >> 8; in aty128_init()
1914 video_card[9] = ent->device & 0xFF; in aty128_init()
1917 if (ent->driver_data < ARRAY_SIZE(r128_family)) in aty128_init()
1918 strlcat(video_card, r128_family[ent->driver_data], in aty128_init()
1921 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); in aty128_init()
1923 if (par->vram_size % (1024 * 1024) == 0) in aty128_init()
1924 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); in aty128_init()
1926 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); in aty128_init()
1928 par->chip_gen = ent->driver_data; in aty128_init()
1931 info->fbops = &aty128fb_ops; in aty128_init()
1932 info->flags = FBINFO_FLAG_DEFAULT; in aty128_init()
1934 par->lcd_on = default_lcd_on; in aty128_init()
1935 par->crt_on = default_crt_on; in aty128_init()
1941 if (par->chip_gen == rage_M3) { in aty128_init()
1942 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); in aty128_init()
1943 #if 0 /* Disable the early video resume hack for now as it's causing problems, in aty128_init()
1958 if (default_vmode <= 0 || default_vmode > VMODE_MAX) in aty128_init()
1999 0, &defaultmode, 8) == 0) in aty128_init()
2008 return 0; in aty128_init()
2015 if (par->chip_gen == rage_M3) in aty128_init()
2022 info->var = var; in aty128_init()
2023 fb_alloc_cmap(&info->cmap, 256, 0); in aty128_init()
2029 par->pdev = pdev; in aty128_init()
2030 par->asleep = 0; in aty128_init()
2031 par->lock_blank = 0; in aty128_init()
2038 if (register_framebuffer(info) < 0) in aty128_init()
2039 return 0; in aty128_init()
2042 info->fix.id, video_card); in aty128_init()
2067 return -ENODEV; in aty128_probe()
2070 fb_addr = pci_resource_start(pdev, 0); in aty128_probe()
2071 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), in aty128_probe()
2075 return -ENODEV; in aty128_probe()
2086 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); in aty128_probe()
2090 par = info->par; in aty128_probe()
2092 info->pseudo_palette = par->pseudo_palette; in aty128_probe()
2095 info->fix.mmio_start = reg_addr; in aty128_probe()
2096 par->regbase = pci_ioremap_bar(pdev, 2); in aty128_probe()
2097 if (!par->regbase) in aty128_probe()
2102 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; in aty128_probe()
2105 info->screen_base = ioremap_wc(fb_addr, par->vram_size); in aty128_probe()
2106 if (!info->screen_base) in aty128_probe()
2109 /* Set up info->fix */ in aty128_probe()
2110 info->fix = aty128fb_fix; in aty128_probe()
2111 info->fix.smem_start = fb_addr; in aty128_probe()
2112 info->fix.smem_len = par->vram_size; in aty128_probe()
2113 info->fix.mmio_start = reg_addr; in aty128_probe()
2143 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in aty128_probe()
2144 par->vram_size); in aty128_probe()
2145 return 0; in aty128_probe()
2148 iounmap(info->screen_base); in aty128_probe()
2150 iounmap(par->regbase); in aty128_probe()
2157 release_mem_region(pci_resource_start(pdev, 0), in aty128_probe()
2158 pci_resource_len(pdev, 0)); in aty128_probe()
2159 return -ENODEV; in aty128_probe()
2170 par = info->par; in aty128_remove()
2175 aty128_bl_exit(info->bl_dev); in aty128_remove()
2178 arch_phys_wc_del(par->wc_cookie); in aty128_remove()
2179 iounmap(par->regbase); in aty128_remove()
2180 iounmap(info->screen_base); in aty128_remove()
2182 release_mem_region(pci_resource_start(pdev, 0), in aty128_remove()
2183 pci_resource_len(pdev, 0)); in aty128_remove()
2197 struct aty128fb_par *par = fb->par; in aty128fb_blank()
2200 if (par->lock_blank || par->asleep) in aty128fb_blank()
2201 return 0; in aty128fb_blank()
2218 state = 0; in aty128fb_blank()
2223 if (par->chip_gen == rage_M3) { in aty128fb_blank()
2224 aty128_set_crt_enable(par, par->crt_on && !blank); in aty128fb_blank()
2225 aty128_set_lcd_enable(par, par->lcd_on && !blank); in aty128fb_blank()
2228 return 0; in aty128fb_blank()
2234 * entries in the var structure). Return != 0 for invalid regno.
2239 struct aty128fb_par *par = info->par; in aty128fb_setcolreg()
2242 || (par->crtc.depth == 16 && regno > 63) in aty128fb_setcolreg()
2243 || (par->crtc.depth == 15 && regno > 31)) in aty128fb_setcolreg()
2252 u32 *pal = info->pseudo_palette; in aty128fb_setcolreg()
2254 switch (par->crtc.depth) { in aty128fb_setcolreg()
2271 if (par->crtc.depth == 16 && regno > 0) { in aty128fb_setcolreg()
2273 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we in aty128fb_setcolreg()
2279 par->green[regno] = green; in aty128fb_setcolreg()
2281 par->red[regno] = red; in aty128fb_setcolreg()
2282 par->blue[regno] = blue; in aty128fb_setcolreg()
2283 aty128_st_pal(regno * 8, red, par->green[regno*2], in aty128fb_setcolreg()
2286 red = par->red[regno/2]; in aty128fb_setcolreg()
2287 blue = par->blue[regno/2]; in aty128fb_setcolreg()
2289 } else if (par->crtc.bpp == 16) in aty128fb_setcolreg()
2293 return 0; in aty128fb_setcolreg()
2296 #define ATY_MIRROR_LCD_ON 0x00000001
2297 #define ATY_MIRROR_CRT_ON 0x00000002
2299 /* out param: u32* backlight value: 0 to 15 */
2301 /* in param: u32* backlight value: 0 to 15 */
2306 struct aty128fb_par *par = info->par; in aty128fb_ioctl()
2312 if (par->chip_gen != rage_M3) in aty128fb_ioctl()
2313 return -EINVAL; in aty128fb_ioctl()
2317 par->lcd_on = (value & 0x01) != 0; in aty128fb_ioctl()
2318 par->crt_on = (value & 0x02) != 0; in aty128fb_ioctl()
2319 if (!par->crt_on && !par->lcd_on) in aty128fb_ioctl()
2320 par->lcd_on = 1; in aty128fb_ioctl()
2321 aty128_set_crt_enable(par, par->crt_on); in aty128fb_ioctl()
2322 aty128_set_lcd_enable(par, par->lcd_on); in aty128fb_ioctl()
2323 return 0; in aty128fb_ioctl()
2325 if (par->chip_gen != rage_M3) in aty128fb_ioctl()
2326 return -EINVAL; in aty128fb_ioctl()
2327 value = (par->crt_on << 1) | par->lcd_on; in aty128fb_ioctl()
2330 return -EINVAL; in aty128fb_ioctl()
2337 if (!par->pdev->pm_cap) in aty128_set_suspend()
2341 * D3 would require a complete re-initialisation of the chip, in aty128_set_suspend()
2356 pmgt = 0x0c005407; in aty128_set_suspend()
2359 aty_st_le32(BUS_CNTL1, 0x00000010); in aty128_set_suspend()
2360 aty_st_le32(MEM_POWER_MISC, 0x0c830000); in aty128_set_suspend()
2369 struct aty128fb_par *par = info->par; in aty128_pci_suspend_late()
2371 /* We don't do anything but D2, for now we return 0, but in aty128_pci_suspend_late()
2382 return 0; in aty128_pci_suspend_late()
2385 if (state.event == pdev->dev.power.power_state.event) in aty128_pci_suspend_late()
2386 return 0; in aty128_pci_suspend_late()
2403 par->asleep = 1; in aty128_pci_suspend_late()
2404 par->lock_blank = 1; in aty128_pci_suspend_late()
2424 pdev->dev.power.power_state = state; in aty128_pci_suspend_late()
2426 return 0; in aty128_pci_suspend_late()
2447 struct aty128fb_par *par = info->par; in aty128_do_resume()
2449 if (pdev->dev.power.power_state.event == PM_EVENT_ON) in aty128_do_resume()
2450 return 0; in aty128_do_resume()
2458 aty128_set_suspend(par, 0); in aty128_do_resume()
2459 par->asleep = 0; in aty128_do_resume()
2465 fb_pan_display(info, &info->var); in aty128_do_resume()
2466 fb_set_cmap(&info->cmap, info); in aty128_do_resume()
2469 fb_set_suspend(info, 0); in aty128_do_resume()
2472 par->lock_blank = 0; in aty128_do_resume()
2473 aty128fb_blank(0, info); in aty128_do_resume()
2483 pdev->dev.power.power_state = PMSG_ON; in aty128_do_resume()
2487 return 0; in aty128_do_resume()
2508 return -ENODEV; in aty128fb_init()
2524 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2527 module_param(mode_option, charp, 0);
2528 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2529 module_param_named(nomtrr, mtrr, invbool, 0);
2530 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");