34 #define XR21V141X_UART_REG_BLOCK	0
36 #define XR21V141X_UART_CUSTOM_BLOCK	0x66
39 #define XR21V141X_CLOCK_DIVISOR_0	0x04
40 #define XR21V141X_CLOCK_DIVISOR_1	0x05
41 #define XR21V141X_CLOCK_DIVISOR_2	0x06
42 #define XR21V141X_TX_CLOCK_MASK_0	0x07
43 #define XR21V141X_TX_CLOCK_MASK_1	0x08
44 #define XR21V141X_RX_CLOCK_MASK_0	0x09
45 #define XR21V141X_RX_CLOCK_MASK_1	0x0a
46 #define XR21V141X_REG_FORMAT		0x0b
49 #define XR21V141X_UM_FIFO_ENABLE_REG	0x10
50 #define XR21V141X_UM_ENABLE_TX_FIFO	0x01
51 #define XR21V141X_UM_ENABLE_RX_FIFO	0x02
53 #define XR21V141X_UM_RX_FIFO_RESET	0x18
54 #define XR21V141X_UM_TX_FIFO_RESET	0x1c
56 #define XR_UART_ENABLE_TX		0x1
57 #define XR_UART_ENABLE_RX		0x2
59 #define XR_GPIO_RI			BIT(0)
70 #define XR_UART_DATA_MASK		GENMASK(3, 0)
71 #define XR_UART_DATA_7			0x7
72 #define XR_UART_DATA_8			0x8
76 #define XR_UART_PARITY_NONE		(0x0 << XR_UART_PARITY_SHIFT)
77 #define XR_UART_PARITY_ODD		(0x1 << XR_UART_PARITY_SHIFT)
78 #define XR_UART_PARITY_EVEN		(0x2 <<	XR_UART_PARITY_SHIFT)
79 #define XR_UART_PARITY_MARK		(0x3 << XR_UART_PARITY_SHIFT)
80 #define XR_UART_PARITY_SPACE		(0x4 << XR_UART_PARITY_SHIFT)
84 #define XR_UART_STOP_1			(0x0 << XR_UART_STOP_SHIFT)
85 #define XR_UART_STOP_2			(0x1 << XR_UART_STOP_SHIFT)
87 #define XR_UART_FLOW_MODE_NONE		0x0
88 #define XR_UART_FLOW_MODE_HW		0x1
89 #define XR_UART_FLOW_MODE_SW		0x2
91 #define XR_GPIO_MODE_SEL_MASK		GENMASK(2, 0)
92 #define XR_GPIO_MODE_SEL_RTS_CTS	0x1
93 #define XR_GPIO_MODE_SEL_DTR_DSR	0x2
94 #define XR_GPIO_MODE_SEL_RS485		0x3
95 #define XR_GPIO_MODE_SEL_RS485_ADDR	0x4
96 #define XR_GPIO_MODE_TX_TOGGLE		0x100
97 #define XR_GPIO_MODE_RX_TOGGLE		0x200
99 #define XR_FIFO_RESET			0x1
101 #define XR_CUSTOM_DRIVER_ACTIVE		0x1
153 		.set_reg	= 0x00,
154 		.get_reg	= 0x01,
156 		.uart_enable	= 0x03,
157 		.flow_control	= 0x0c,
158 		.xon_char	= 0x10,
159 		.xoff_char	= 0x11,
160 		.tx_break	= 0x14,
161 		.gpio_mode	= 0x1a,
162 		.gpio_direction	= 0x1b,
163 		.gpio_set	= 0x1d,
164 		.gpio_clear	= 0x1e,
165 		.gpio_status	= 0x1f,
175 		.set_reg	= 0x00,
176 		.get_reg	= 0x00,
178 		.uart_enable	= 0x00,
179 		.flow_control	= 0x06,
180 		.xon_char	= 0x07,
181 		.xoff_char	= 0x08,
182 		.tx_break	= 0x0a,
183 		.gpio_mode	= 0x0c,
184 		.gpio_direction	= 0x0d,
185 		.gpio_set	= 0x0e,
186 		.gpio_clear	= 0x0f,
187 		.gpio_status	= 0x10,
188 		.tx_fifo_reset	= 0x40,
189 		.rx_fifo_reset	= 0x43,
190 		.custom_driver	= 0x60,
198 		.set_reg	= 0x00,
199 		.get_reg	= 0x01,
201 		.uart_enable	= 0xc00,
202 		.flow_control	= 0xc06,
203 		.xon_char	= 0xc07,
204 		.xoff_char	= 0xc08,
205 		.tx_break	= 0xc0a,
206 		.gpio_mode	= 0xc0c,
207 		.gpio_direction	= 0xc0d,
208 		.gpio_set	= 0xc0e,
209 		.gpio_clear	= 0xc0f,
210 		.gpio_status	= 0xc10,
211 		.tx_fifo_reset	= 0xc80,
212 		.rx_fifo_reset	= 0xcc0,
213 		.custom_driver	= 0x20d,
218 		.set_reg	= 0x05,
219 		.get_reg	= 0x05,
221 		.uart_enable	= 0x40,
222 		.flow_control	= 0x46,
223 		.xon_char	= 0x47,
224 		.xoff_char	= 0x48,
225 		.tx_break	= 0x4a,
226 		.gpio_mode	= 0x4c,
227 		.gpio_direction	= 0x4d,
228 		.gpio_set	= 0x4e,
229 		.gpio_clear	= 0x4f,
230 		.gpio_status	= 0x50,
231 		.tx_fifo_reset	= 0x60,
232 		.rx_fifo_reset	= 0x63,
233 		.custom_driver	= 0x81,
249 	ret = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0),  in xr_set_reg()
252 			val, (channel << 8) | reg, NULL, 0,  in xr_set_reg()
254 	if (ret < 0) {  in xr_set_reg()
255 		dev_err(&port->dev, "Failed to set reg 0x%02x: %d\n", reg, ret);  in xr_set_reg()
259 	return 0;  in xr_set_reg()
279 	ret = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),  in xr_get_reg()
282 			0, (channel << 8) | reg, dmabuf, len,  in xr_get_reg()
289 		ret = 0;  in xr_get_reg()
291 		dev_err(&port->dev, "Failed to get reg 0x%02x: %d\n", reg, ret);  in xr_get_reg()
292 		if (ret >= 0)  in xr_get_reg()
337 	return xr_set_reg_uart(port, data->type->uart_enable, 0);  in __xr_uart_disable()
377 	ret = xr_set_reg_um(port, XR21V141X_UM_FIFO_ENABLE_REG, 0);  in xr21v141x_uart_disable()
414 	return 0;  in xr21v141x_fifo_reset()
433 	return 0;  in xr_fifo_reset()
448 	 * Modem control pins are active low, so reading '0' means it is active  in xr_tiocmget()
451 	ret = ((status & XR_GPIO_DTR) ? 0 : TIOCM_DTR) |  in xr_tiocmget()
452 	      ((status & XR_GPIO_RTS) ? 0 : TIOCM_RTS) |  in xr_tiocmget()
453 	      ((status & XR_GPIO_CTS) ? 0 : TIOCM_CTS) |  in xr_tiocmget()
454 	      ((status & XR_GPIO_DSR) ? 0 : TIOCM_DSR) |  in xr_tiocmget()
455 	      ((status & XR_GPIO_RI) ? 0 : TIOCM_RI) |  in xr_tiocmget()
456 	      ((status & XR_GPIO_CD) ? 0 : TIOCM_CD);  in xr_tiocmget()
466 	u16 gpio_set = 0;  in xr_tiocmset_port()
467 	u16 gpio_clr = 0;  in xr_tiocmset_port()
468 	int ret = 0;  in xr_tiocmset_port()
480 	/* Writing '0' to gpio_{set/clr} bits has no effect, so no need to do */  in xr_tiocmset_port()
501 		xr_tiocmset_port(port, TIOCM_DTR | TIOCM_RTS, 0);  in xr_dtr_rts()
503 		xr_tiocmset_port(port, 0, TIOCM_DTR | TIOCM_RTS);  in xr_dtr_rts()
513 	if (break_state == 0)  in xr_break_ctl()
514 		state = 0;  in xr_break_ctl()
516 		state = GENMASK(type->reg_width - 1, 0);  in xr_break_ctl()
518 	dev_dbg(&port->dev, "Turning break %s\n", state == 0 ? "off" : "on");  in xr_break_ctl()
525 	{ 0x000, 0x000, 0x000 },
526 	{ 0x000, 0x000, 0x000 },
527 	{ 0x100, 0x000, 0x100 },
528 	{ 0x020, 0x400, 0x020 },
529 	{ 0x010, 0x100, 0x010 },
530 	{ 0x208, 0x040, 0x208 },
531 	{ 0x104, 0x820, 0x108 },
532 	{ 0x844, 0x210, 0x884 },
533 	{ 0x444, 0x110, 0x444 },
534 	{ 0x122, 0x888, 0x224 },
535 	{ 0x912, 0x448, 0x924 },
536 	{ 0x492, 0x248, 0x492 },
537 	{ 0x252, 0x928, 0x292 },
538 	{ 0x94a, 0x4a4, 0xa52 },
539 	{ 0x52a, 0xaa4, 0x54a },
540 	{ 0xaaa, 0x954, 0x4aa },
541 	{ 0xaaa, 0x554, 0xaaa },
542 	{ 0x555, 0xad4, 0x5aa },
543 	{ 0xb55, 0xab4, 0x55a },
544 	{ 0x6b5, 0x5ac, 0xb56 },
545 	{ 0x5b5, 0xd6c, 0x6d6 },
546 	{ 0xb6d, 0xb6a, 0xdb6 },
547 	{ 0x76d, 0x6da, 0xbb6 },
548 	{ 0xedd, 0xdda, 0x76e },
549 	{ 0xddd, 0xbba, 0xeee },
550 	{ 0x7bb, 0xf7a, 0xdde },
551 	{ 0xf7b, 0xef6, 0x7de },
552 	{ 0xdf7, 0xbf6, 0xf7e },
553 	{ 0x7f7, 0xfee, 0xefe },
554 	{ 0xfdf, 0xfbe, 0x7fe },
555 	{ 0xf7f, 0xefe, 0xffe },
556 	{ 0xfff, 0xffe, 0xffd },
567 		return 0;  in xr21v141x_set_baudrate()
571 	idx = ((32 * XR_INT_OSC_HZ) / baud) & 0x1f;  in xr21v141x_set_baudrate()
574 	if (divisor & 0x01)  in xr21v141x_set_baudrate()
586 			      divisor & 0xff);  in xr21v141x_set_baudrate()
591 			      (divisor >>  8) & 0xff);  in xr21v141x_set_baudrate()
596 			      (divisor >> 16) & 0xff);  in xr21v141x_set_baudrate()
601 			      tx_mask & 0xff);  in xr21v141x_set_baudrate()
606 			      (tx_mask >>  8) & 0xff);  in xr21v141x_set_baudrate()
611 			      rx_mask & 0xff);  in xr21v141x_set_baudrate()
616 			      (rx_mask >>  8) & 0xff);  in xr21v141x_set_baudrate()
622 	return 0;  in xr21v141x_set_baudrate()
672 		xr_dtr_rts(port, 0);  in xr_set_flow_mode()
682 	u8 bits = 0;  in xr21v141x_set_line_settings()
803 	ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),  in xr_cdc_set_line_coding()
806 			0, alt->desc.bInterfaceNumber,  in xr_cdc_set_line_coding()
808 	if (ret < 0)  in xr_cdc_set_line_coding()
856 	return 0;  in xr_open()
876 	if (ret < 0)  in xr_probe()
893 	return 0;  in xr_probe()
904 	mode = 0;  in xr_gpio_init()
925 	return 0;  in xr_gpio_init()
964 	return 0;  in xr_port_probe()
984 	{ XR_DEVICE(0x04e2, 0x1400, XR2280X) },
985 	{ XR_DEVICE(0x04e2, 0x1401, XR2280X) },
986 	{ XR_DEVICE(0x04e2, 0x1402, XR2280X) },
987 	{ XR_DEVICE(0x04e2, 0x1403, XR2280X) },
988 	{ XR_DEVICE(0x04e2, 0x1410, XR21V141X) },
989 	{ XR_DEVICE(0x04e2, 0x1411, XR21B1411) },
990 	{ XR_DEVICE(0x04e2, 0x1412, XR21V141X) },
991 	{ XR_DEVICE(0x04e2, 0x1414, XR21V141X) },
992 	{ XR_DEVICE(0x04e2, 0x1420, XR21B142X) },
993 	{ XR_DEVICE(0x04e2, 0x1422, XR21B142X) },
994 	{ XR_DEVICE(0x04e2, 0x1424, XR21B142X) },