Lines Matching +full:last +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
73 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
74 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
75 #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes
76 #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes
77 #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level
78 #define FCR_RX_LEVEL_8 0x00 // Rx FIFO Level = 8 bytes
79 #define FCR_RX_LEVEL_16 0x40 // Rx FIFO Level = 16 bytes
80 #define FCR_RX_LEVEL_56 0x80 // Rx FIFO Level = 56 bytes
81 #define FCR_RX_LEVEL_60 0xC0 // Rx FIFO Level = 60 bytes
104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
118 // and also the '654-only registers
142 #define EDGEPORT_MSR_DELTA_CTS 0x01 // CTS changed from last read
143 #define EDGEPORT_MSR_DELTA_DSR 0x02 // DSR changed from last read
144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
145 #define EDGEPORT_MSR_DELTA_CD 0x08 // CD changed from last read
154 //-------------------------------