Lines Matching +full:0 +full:x102
13 #define LPSTS 0x102
14 #define UGCTRL 0x180 /* 32-bit register */
15 #define UGCTRL2 0x184 /* 32-bit register */
16 #define UGSTS 0x188 /* 32-bit register */
19 #define LPSTS_SUSPM 0x4000
22 #define UGCTRL_PLLRESET 0x00000001
23 #define UGCTRL_CONNECT 0x00000004
27 * Remarks: bit[31:11] and bit[9:6] should be 0
29 #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
30 #define UGCTRL2_USB0SEL_HSUSB 0x00000020
31 #define UGCTRL2_USB0SEL_OTG 0x00000030
32 #define UGCTRL2_VBUSSEL 0x00000400
35 #define UGSTS_LOCK 0x00000100
64 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0); in usbhs_rcar3_power_ctrl()
67 return 0; in usbhs_rcar3_power_ctrl()
79 usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */ in usbhs_rcar3_power_and_pll_ctrl()
90 usbhs_write32(priv, UGCTRL, 0); in usbhs_rcar3_power_and_pll_ctrl()
91 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0); in usbhs_rcar3_power_and_pll_ctrl()
95 return 0; in usbhs_rcar3_power_and_pll_ctrl()