Lines Matching +full:toggle +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/dma-mapping.h>
24 /* MUSB HOST status 22-mar-2006
26 * - There's still lots of partial code duplication for fault paths, so
29 * - PIO mostly behaved when last tested.
36 * - DMA (CPPI) ... partially behaves, not currently recommended
41 * - DMA (Mentor/OMAP) ...has at least toggle update problems
43 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
46 * - Not tested with HNP, but some SRP paths seem to behave.
48 * NOTE 24-August-2006:
50 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
53 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
54 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
75 return *(struct musb **) hcd->hcd_priv; in hcd_to_musb()
88 struct musb *musb = ep->musb; in musb_h_tx_flush_fifo()
89 void __iomem *epio = ep->regs; in musb_h_tx_flush_fifo()
107 * I found using a usb-ethernet device and running iperf in musb_h_tx_flush_fifo()
113 if (dev_WARN_ONCE(musb->controller, retries-- < 1, in musb_h_tx_flush_fifo()
115 ep->epnum, csr)) in musb_h_tx_flush_fifo()
123 void __iomem *epio = ep->regs; in musb_h_ep0_flush_fifo()
135 } while (--retries); in musb_h_ep0_flush_fifo()
138 ep->epnum, csr); in musb_h_ep0_flush_fifo()
153 if (ep->epnum) { in musb_h_tx_start()
154 txcsr = musb_readw(ep->regs, MUSB_TXCSR); in musb_h_tx_start()
156 musb_writew(ep->regs, MUSB_TXCSR, txcsr); in musb_h_tx_start()
159 musb_writew(ep->regs, MUSB_CSR0, txcsr); in musb_h_tx_start()
169 txcsr = musb_readw(ep->regs, MUSB_TXCSR); in musb_h_tx_dma_start()
171 if (is_cppi_enabled(ep->musb)) in musb_h_tx_dma_start()
173 musb_writew(ep->regs, MUSB_TXCSR, txcsr); in musb_h_tx_dma_start()
178 if (is_in != 0 || ep->is_shared_fifo) in musb_ep_set_qh()
179 ep->in_qh = qh; in musb_ep_set_qh()
180 if (is_in == 0 || ep->is_shared_fifo) in musb_ep_set_qh()
181 ep->out_qh = qh; in musb_ep_set_qh()
186 return is_in ? ep->in_qh : ep->out_qh; in musb_ep_get_qh()
199 void __iomem *mbase = musb->mregs; in musb_start_urb()
201 void *buf = urb->transfer_buffer; in musb_start_urb()
203 struct musb_hw_ep *hw_ep = qh->hw_ep; in musb_start_urb()
204 int epnum = hw_ep->epnum; in musb_start_urb()
207 qh->offset = 0; in musb_start_urb()
208 qh->segsize = 0; in musb_start_urb()
211 switch (qh->type) { in musb_start_urb()
215 musb->ep0_stage = MUSB_EP0_START; in musb_start_urb()
216 buf = urb->setup_packet; in musb_start_urb()
220 qh->iso_idx = 0; in musb_start_urb()
221 qh->frame = 0; in musb_start_urb()
222 offset = urb->iso_frame_desc[0].offset; in musb_start_urb()
223 len = urb->iso_frame_desc[0].length; in musb_start_urb()
227 buf = urb->transfer_buffer + urb->actual_length; in musb_start_urb()
228 len = urb->transfer_buffer_length - urb->actual_length; in musb_start_urb()
242 switch (qh->type) { in musb_start_urb()
251 * this code; and we don't init urb->start_frame... in musb_start_urb()
253 qh->frame = 0; in musb_start_urb()
256 qh->frame = urb->start_frame; in musb_start_urb()
267 hw_ep->tx_channel ? "dma" : "pio"); in musb_start_urb()
269 if (!hw_ep->tx_channel) in musb_start_urb()
278 __releases(musb->lock) in musb_giveback()
279 __acquires(musb->lock) in musb_giveback()
283 usb_hcd_unlink_urb_from_ep(musb->hcd, urb); in musb_giveback()
284 spin_unlock(&musb->lock); in musb_giveback()
285 usb_hcd_giveback_urb(musb->hcd, urb, status); in musb_giveback()
286 spin_lock(&musb->lock); in musb_giveback()
300 struct musb_hw_ep *ep = qh->hw_ep; in musb_advance_schedule()
301 int ready = qh->is_ready; in musb_advance_schedule()
303 u16 toggle; in musb_advance_schedule() local
305 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; in musb_advance_schedule()
307 /* save toggle eagerly, for paranoia */ in musb_advance_schedule()
308 switch (qh->type) { in musb_advance_schedule()
311 toggle = musb->io.get_toggle(qh, !is_in); in musb_advance_schedule()
312 usb_settoggle(urb->dev, qh->epnum, !is_in, toggle ? 1 : 0); in musb_advance_schedule()
315 if (status == 0 && urb->error_count) in musb_advance_schedule()
316 status = -EXDEV; in musb_advance_schedule()
320 qh->is_ready = 0; in musb_advance_schedule()
322 qh->is_ready = ready; in musb_advance_schedule()
325 * invalidate qh as soon as list_empty(&hep->urb_list) in musb_advance_schedule()
327 if (list_empty(&qh->hep->urb_list)) { in musb_advance_schedule()
329 struct dma_controller *dma = musb->dma_controller; in musb_advance_schedule()
332 ep->rx_reinit = 1; in musb_advance_schedule()
333 if (ep->rx_channel) { in musb_advance_schedule()
334 dma->channel_release(ep->rx_channel); in musb_advance_schedule()
335 ep->rx_channel = NULL; in musb_advance_schedule()
338 ep->tx_reinit = 1; in musb_advance_schedule()
339 if (ep->tx_channel) { in musb_advance_schedule()
340 dma->channel_release(ep->tx_channel); in musb_advance_schedule()
341 ep->tx_channel = NULL; in musb_advance_schedule()
347 qh->hep->hcpriv = NULL; in musb_advance_schedule()
349 switch (qh->type) { in musb_advance_schedule()
356 if (qh->mux == 1) { in musb_advance_schedule()
357 head = qh->ring.prev; in musb_advance_schedule()
358 list_del(&qh->ring); in musb_advance_schedule()
368 * de-allocated if it's tracked and allocated; in musb_advance_schedule()
377 if (qh != NULL && qh->is_ready) { in musb_advance_schedule()
379 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); in musb_advance_schedule()
388 * leave toggle alone (may not have been saved yet) in musb_h_flush_rxfifo()
396 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
397 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
400 return musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_h_flush_rxfifo()
415 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_packet_rx()
416 void __iomem *epio = hw_ep->regs; in musb_host_packet_rx()
417 struct musb_qh *qh = hw_ep->in_qh; in musb_host_packet_rx()
418 int pipe = urb->pipe; in musb_host_packet_rx()
419 void *buffer = urb->transfer_buffer; in musb_host_packet_rx()
424 urb->transfer_buffer, qh->offset, in musb_host_packet_rx()
425 urb->transfer_buffer_length); in musb_host_packet_rx()
433 status = -EILSEQ; in musb_host_packet_rx()
434 urb->error_count++; in musb_host_packet_rx()
437 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_packet_rx()
438 buf = buffer + d->offset; in musb_host_packet_rx()
439 length = d->length; in musb_host_packet_rx()
442 status = -EOVERFLOW; in musb_host_packet_rx()
443 urb->error_count++; in musb_host_packet_rx()
449 urb->actual_length += length; in musb_host_packet_rx()
450 d->actual_length = length; in musb_host_packet_rx()
452 d->status = status; in musb_host_packet_rx()
455 done = (++qh->iso_idx >= urb->number_of_packets); in musb_host_packet_rx()
457 /* non-isoch */ in musb_host_packet_rx()
458 buf = buffer + qh->offset; in musb_host_packet_rx()
459 length = urb->transfer_buffer_length - qh->offset; in musb_host_packet_rx()
461 if (urb->status == -EINPROGRESS) in musb_host_packet_rx()
462 urb->status = -EOVERFLOW; in musb_host_packet_rx()
467 urb->actual_length += length; in musb_host_packet_rx()
468 qh->offset += length; in musb_host_packet_rx()
471 done = (urb->actual_length == urb->transfer_buffer_length) in musb_host_packet_rx()
472 || (rx_count < qh->maxpacket) in musb_host_packet_rx()
473 || (urb->status != -EINPROGRESS); in musb_host_packet_rx()
475 && (urb->status == -EINPROGRESS) in musb_host_packet_rx()
476 && (urb->transfer_flags & URB_SHORT_NOT_OK) in musb_host_packet_rx()
477 && (urb->actual_length in musb_host_packet_rx()
478 < urb->transfer_buffer_length)) in musb_host_packet_rx()
479 urb->status = -EREMOTEIO; in musb_host_packet_rx()
501 * to address data toggle, NYET, and DMA or PIO.
505 * the busy/not-empty tests are basically paranoia.
510 struct musb_hw_ep *ep = musb->endpoints + epnum; in musb_rx_reinit()
518 /* if programmed for Tx, put it in RX mode */ in musb_rx_reinit()
519 if (ep->is_shared_fifo) { in musb_rx_reinit()
520 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
523 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
524 musb_writew(ep->regs, MUSB_TXCSR, in musb_rx_reinit()
529 * Clear the MODE bit (and everything else) to enable Rx. in musb_rx_reinit()
533 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); in musb_rx_reinit()
534 musb_writew(ep->regs, MUSB_TXCSR, 0); in musb_rx_reinit()
536 /* scrub all previous state, clearing toggle */ in musb_rx_reinit()
538 csr = musb_readw(ep->regs, MUSB_RXCSR); in musb_rx_reinit()
540 WARNING("rx%d, packet/%d ready?\n", ep->epnum, in musb_rx_reinit()
541 musb_readw(ep->regs, MUSB_RXCOUNT)); in musb_rx_reinit()
546 if (musb->is_multipoint) { in musb_rx_reinit()
547 musb_write_rxfunaddr(musb, epnum, qh->addr_reg); in musb_rx_reinit()
548 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg); in musb_rx_reinit()
549 musb_write_rxhubport(musb, epnum, qh->h_port_reg); in musb_rx_reinit()
551 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); in musb_rx_reinit()
554 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); in musb_rx_reinit()
555 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); in musb_rx_reinit()
558 * to disable double buffer mode. in musb_rx_reinit()
560 musb_writew(ep->regs, MUSB_RXMAXP, in musb_rx_reinit()
561 qh->maxpacket | ((qh->hb_mult - 1) << 11)); in musb_rx_reinit()
563 ep->rx_reinit = 0; in musb_rx_reinit()
568 u32 *length, u8 *mode) in musb_tx_dma_set_mode_mentor() argument
570 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_set_mode_mentor()
571 void __iomem *epio = hw_ep->regs; in musb_tx_dma_set_mode_mentor()
572 u16 pkt_size = qh->maxpacket; in musb_tx_dma_set_mode_mentor()
575 if (*length > channel->max_len) in musb_tx_dma_set_mode_mentor()
576 *length = channel->max_len; in musb_tx_dma_set_mode_mentor()
580 *mode = 1; in musb_tx_dma_set_mode_mentor()
592 if (qh->hb_mult == 1 || (qh->hb_mult > 1 && in musb_tx_dma_set_mode_mentor()
593 can_bulk_split(hw_ep->musb, qh->type))) in musb_tx_dma_set_mode_mentor()
596 *mode = 0; in musb_tx_dma_set_mode_mentor()
600 channel->desired_mode = *mode; in musb_tx_dma_set_mode_mentor()
606 u8 *mode) in musb_tx_dma_set_mode_cppi_tusb() argument
608 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_set_mode_cppi_tusb()
610 channel->actual_len = 0; in musb_tx_dma_set_mode_cppi_tusb()
613 * TX uses "RNDIS" mode automatically but needs help in musb_tx_dma_set_mode_cppi_tusb()
614 * to identify the zero-length-final-packet case. in musb_tx_dma_set_mode_cppi_tusb()
616 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; in musb_tx_dma_set_mode_cppi_tusb()
623 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_program()
624 u16 pkt_size = qh->maxpacket; in musb_tx_dma_program()
625 u8 mode; in musb_tx_dma_program() local
627 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb)) in musb_tx_dma_program()
629 &length, &mode); in musb_tx_dma_program()
630 else if (is_cppi_enabled(hw_ep->musb) || tusb_dma_omap(hw_ep->musb)) in musb_tx_dma_program()
631 musb_tx_dma_set_mode_cppi_tusb(hw_ep, urb, &mode); in musb_tx_dma_program()
635 qh->segsize = length; in musb_tx_dma_program()
643 if (!dma->channel_program(channel, pkt_size, mode, in musb_tx_dma_program()
644 urb->transfer_dma + offset, length)) { in musb_tx_dma_program()
645 void __iomem *epio = hw_ep->regs; in musb_tx_dma_program()
648 dma->channel_release(channel); in musb_tx_dma_program()
649 hw_ep->tx_channel = NULL; in musb_tx_dma_program()
670 void __iomem *mbase = musb->mregs; in musb_ep_program()
671 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_ep_program()
672 void __iomem *epio = hw_ep->regs; in musb_ep_program()
674 u16 packet_sz = qh->maxpacket; in musb_ep_program()
680 is_out ? "-->" : "<--", in musb_ep_program()
681 epnum, urb, urb->dev->speed, in musb_ep_program()
682 qh->addr_reg, qh->epnum, is_out ? "out" : "in", in musb_ep_program()
683 qh->h_addr_reg, qh->h_port_reg, in musb_ep_program()
693 hw_ep->tx_channel = NULL; in musb_ep_program()
697 dma_controller = musb->dma_controller; in musb_ep_program()
699 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; in musb_ep_program()
701 dma_channel = dma_controller->channel_alloc( in musb_ep_program()
704 hw_ep->tx_channel = dma_channel; in musb_ep_program()
706 hw_ep->rx_channel = dma_channel; in musb_ep_program()
722 int_txe = musb->intrtxe; in musb_ep_program()
733 if (!hw_ep->tx_double_buffered) in musb_ep_program()
751 if (!hw_ep->tx_double_buffered) in musb_ep_program()
752 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
765 if (musb->is_multipoint) { in musb_ep_program()
766 musb_write_txfunaddr(musb, epnum, qh->addr_reg); in musb_ep_program()
767 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg); in musb_ep_program()
768 musb_write_txhubport(musb, epnum, qh->h_port_reg); in musb_ep_program()
771 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); in musb_ep_program()
775 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); in musb_ep_program()
776 if (can_bulk_split(musb, qh->type)) { in musb_ep_program()
777 qh->hb_mult = hw_ep->max_packet_sz_tx in musb_ep_program()
780 | ((qh->hb_mult) - 1) << 11); in musb_ep_program()
783 qh->maxpacket | in musb_ep_program()
784 ((qh->hb_mult - 1) << 11)); in musb_ep_program()
786 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); in musb_ep_program()
788 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); in musb_ep_program()
789 if (musb->is_multipoint) in musb_ep_program()
791 qh->type_reg); in musb_ep_program()
794 if (can_bulk_split(musb, qh->type)) in musb_ep_program()
795 load_count = min((u32) hw_ep->max_packet_sz_tx, in musb_ep_program()
806 qh->segsize = load_count; in musb_ep_program()
808 sg_miter_start(&qh->sg_miter, urb->sg, 1, in musb_ep_program()
811 if (!sg_miter_next(&qh->sg_miter)) { in musb_ep_program()
812 dev_err(musb->controller, in musb_ep_program()
815 sg_miter_stop(&qh->sg_miter); in musb_ep_program()
818 buf = qh->sg_miter.addr + urb->sg->offset + in musb_ep_program()
819 urb->actual_length; in musb_ep_program()
821 qh->sg_miter.length); in musb_ep_program()
823 qh->sg_miter.consumed = load_count; in musb_ep_program()
824 sg_miter_stop(&qh->sg_miter); in musb_ep_program()
829 /* re-enable interrupt */ in musb_ep_program()
836 if (hw_ep->rx_reinit) { in musb_ep_program()
838 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
840 if (qh->type == USB_ENDPOINT_XFER_INT) in musb_ep_program()
844 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
850 hw_ep->epnum, csr); in musb_ep_program()
852 /* scrub any stale state, leaving toggle alone */ in musb_ep_program()
860 dma_channel->actual_len = 0L; in musb_ep_program()
861 qh->segsize = len; in musb_ep_program()
864 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
865 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
871 dma_ok = dma_controller->channel_program(dma_channel, in musb_ep_program()
872 packet_sz, !(urb->transfer_flags & in musb_ep_program()
874 urb->transfer_dma + offset, in musb_ep_program()
875 qh->segsize); in musb_ep_program()
877 dma_controller->channel_release(dma_channel); in musb_ep_program()
878 hw_ep->rx_channel = dma_channel = NULL; in musb_ep_program()
885 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
886 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
890 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
898 void __iomem *mbase = musb->mregs; in musb_bulk_nak_timeout()
899 void __iomem *epio = ep->regs; in musb_bulk_nak_timeout()
902 u16 toggle; in musb_bulk_nak_timeout() local
904 musb_ep_select(mbase, ep->epnum); in musb_bulk_nak_timeout()
906 dma = is_dma_capable() ? ep->rx_channel : NULL; in musb_bulk_nak_timeout()
910 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED in musb_bulk_nak_timeout()
911 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2 in musb_bulk_nak_timeout()
920 cur_qh = first_qh(&musb->in_bulk); in musb_bulk_nak_timeout()
922 dma = is_dma_capable() ? ep->tx_channel : NULL; in musb_bulk_nak_timeout()
930 cur_qh = first_qh(&musb->out_bulk); in musb_bulk_nak_timeout()
935 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_bulk_nak_timeout()
936 musb->dma_controller->channel_abort(dma); in musb_bulk_nak_timeout()
937 urb->actual_length += dma->actual_len; in musb_bulk_nak_timeout()
938 dma->actual_len = 0L; in musb_bulk_nak_timeout()
940 toggle = musb->io.get_toggle(cur_qh, !is_in); in musb_bulk_nak_timeout()
941 usb_settoggle(urb->dev, cur_qh->epnum, !is_in, toggle ? 1 : 0); in musb_bulk_nak_timeout()
945 list_move_tail(&cur_qh->ring, &musb->in_bulk); in musb_bulk_nak_timeout()
947 /* get the next qh from musb->in_bulk */ in musb_bulk_nak_timeout()
948 next_qh = first_qh(&musb->in_bulk); in musb_bulk_nak_timeout()
951 ep->rx_reinit = 1; in musb_bulk_nak_timeout()
954 list_move_tail(&cur_qh->ring, &musb->out_bulk); in musb_bulk_nak_timeout()
956 /* get the next qh from musb->out_bulk */ in musb_bulk_nak_timeout()
957 next_qh = first_qh(&musb->out_bulk); in musb_bulk_nak_timeout()
960 ep->tx_reinit = 1; in musb_bulk_nak_timeout()
977 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_continue()
978 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_continue()
981 switch (musb->ep0_stage) { in musb_h_ep0_continue()
983 fifo_dest = urb->transfer_buffer + urb->actual_length; in musb_h_ep0_continue()
984 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - in musb_h_ep0_continue()
985 urb->actual_length); in musb_h_ep0_continue()
987 urb->status = -EOVERFLOW; in musb_h_ep0_continue()
991 urb->actual_length += fifo_count; in musb_h_ep0_continue()
992 if (len < qh->maxpacket) { in musb_h_ep0_continue()
996 } else if (urb->actual_length < in musb_h_ep0_continue()
997 urb->transfer_buffer_length) in musb_h_ep0_continue()
1001 request = (struct usb_ctrlrequest *) urb->setup_packet; in musb_h_ep0_continue()
1003 if (!request->wLength) { in musb_h_ep0_continue()
1004 musb_dbg(musb, "start no-DATA"); in musb_h_ep0_continue()
1006 } else if (request->bRequestType & USB_DIR_IN) { in musb_h_ep0_continue()
1007 musb_dbg(musb, "start IN-DATA"); in musb_h_ep0_continue()
1008 musb->ep0_stage = MUSB_EP0_IN; in musb_h_ep0_continue()
1012 musb_dbg(musb, "start OUT-DATA"); in musb_h_ep0_continue()
1013 musb->ep0_stage = MUSB_EP0_OUT; in musb_h_ep0_continue()
1018 fifo_count = min_t(size_t, qh->maxpacket, in musb_h_ep0_continue()
1019 urb->transfer_buffer_length - in musb_h_ep0_continue()
1020 urb->actual_length); in musb_h_ep0_continue()
1022 fifo_dest = (u8 *) (urb->transfer_buffer in musb_h_ep0_continue()
1023 + urb->actual_length); in musb_h_ep0_continue()
1030 urb->actual_length += fifo_count; in musb_h_ep0_continue()
1035 ERR("bogus ep0 stage %d\n", musb->ep0_stage); in musb_h_ep0_continue()
1053 void __iomem *mbase = musb->mregs; in musb_h_ep0_irq()
1054 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_irq()
1055 void __iomem *epio = hw_ep->regs; in musb_h_ep0_irq()
1056 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_irq()
1070 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
1073 if (MUSB_EP0_STATUS == musb->ep0_stage) { in musb_h_ep0_irq()
1081 status = -EPIPE; in musb_h_ep0_irq()
1085 status = -EPROTO; in musb_h_ep0_irq()
1095 * if (qh->ring.next != &musb->control), then in musb_h_ep0_irq()
1106 urb->status = status; in musb_h_ep0_irq()
1138 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1142 if (usb_pipeout(urb->pipe) in musb_h_ep0_irq()
1143 || !urb->transfer_buffer_length) in musb_h_ep0_irq()
1154 musb->ep0_stage = MUSB_EP0_STATUS; in musb_h_ep0_irq()
1162 musb->ep0_stage = MUSB_EP0_IDLE; in musb_h_ep0_irq()
1175 submit_urb ->
1176 - if queue was empty, Program Endpoint
1177 - ... which starts DMA to fifo in mode 1 or 0
1179 DMA Isr (transfer complete) -> TxAvail()
1180 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1182 - TxPktRdy has to be set in mode 0 or for
1183 short packets in mode 1.
1188 /* Service a Tx-Available or dma completion irq for the endpoint */
1196 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_tx()
1197 void __iomem *epio = hw_ep->regs; in musb_host_tx()
1198 struct musb_qh *qh = hw_ep->out_qh; in musb_host_tx()
1201 void __iomem *mbase = musb->mregs; in musb_host_tx()
1214 pipe = urb->pipe; in musb_host_tx()
1215 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; in musb_host_tx()
1226 status = -EPIPE; in musb_host_tx()
1229 /* (NON-ISO) dma was disabled, fifo flushed */ in musb_host_tx()
1232 status = -ETIMEDOUT; in musb_host_tx()
1235 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 in musb_host_tx()
1236 && !list_is_singular(&musb->out_bulk)) { in musb_host_tx()
1246 * if (bulk && qh->ring.next != &musb->out_bulk), then in musb_host_tx()
1260 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_tx()
1261 musb->dma_controller->channel_abort(dma); in musb_host_tx()
1292 * DMA has completed. But if we're using DMA mode 1 (multi in musb_host_tx()
1296 * switch back to mode 0 to get that interrupt; we'll come in musb_host_tx()
1304 * it being 0 at this moment -- DMA interrupt latency in musb_host_tx()
1307 * programmer's guide... :-) in musb_host_tx()
1310 * in order not to re-trigger the packet send (this bit in musb_host_tx()
1313 * double-buffered FIFO mode, so we do an extra TXCSR in musb_host_tx()
1332 * Re-read TXCSR as we have spoiled its previous value. in musb_host_tx()
1340 * only if the FIFO still has data -- that should prevent the in musb_host_tx()
1341 * "missed" TXPKTRDY interrupts and deal with double-buffered in musb_host_tx()
1342 * FIFO mode too... in musb_host_tx()
1354 length = dma->actual_len; in musb_host_tx()
1356 length = qh->segsize; in musb_host_tx()
1357 qh->offset += length; in musb_host_tx()
1362 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_tx()
1363 d->actual_length = length; in musb_host_tx()
1364 d->status = status; in musb_host_tx()
1365 if (++qh->iso_idx >= urb->number_of_packets) { in musb_host_tx()
1369 offset = d->offset; in musb_host_tx()
1370 length = d->length; in musb_host_tx()
1372 } else if (dma && urb->transfer_buffer_length == qh->offset) { in musb_host_tx()
1376 if (qh->segsize < qh->maxpacket) in musb_host_tx()
1378 else if (qh->offset == urb->transfer_buffer_length in musb_host_tx()
1379 && !(urb->transfer_flags in musb_host_tx()
1383 offset = qh->offset; in musb_host_tx()
1384 length = urb->transfer_buffer_length - offset; in musb_host_tx()
1390 /* urb->status != -EINPROGRESS means request has been faulted, in musb_host_tx()
1393 if (urb->status != -EINPROGRESS) { in musb_host_tx()
1396 status = urb->status; in musb_host_tx()
1401 urb->status = status; in musb_host_tx()
1402 urb->actual_length = qh->offset; in musb_host_tx()
1406 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, in musb_host_tx()
1420 * REVISIT: some docs say that when hw_ep->tx_double_buffered, in musb_host_tx()
1421 * (and presumably, FIFO is not half-full) we should write *two* in musb_host_tx()
1424 if (length > qh->maxpacket) in musb_host_tx()
1425 length = qh->maxpacket; in musb_host_tx()
1427 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); in musb_host_tx()
1433 if (!urb->transfer_buffer) { in musb_host_tx()
1435 if (!sg_miter_next(&qh->sg_miter)) { in musb_host_tx()
1436 dev_err(musb->controller, "error: sg list empty\n"); in musb_host_tx()
1437 sg_miter_stop(&qh->sg_miter); in musb_host_tx()
1438 status = -EINVAL; in musb_host_tx()
1441 length = min_t(u32, length, qh->sg_miter.length); in musb_host_tx()
1442 musb_write_fifo(hw_ep, length, qh->sg_miter.addr); in musb_host_tx()
1443 qh->sg_miter.consumed = length; in musb_host_tx()
1444 sg_miter_stop(&qh->sg_miter); in musb_host_tx()
1446 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); in musb_host_tx()
1449 qh->segsize = length; in musb_host_tx()
1464 struct dma_channel *channel = hw_ep->rx_channel; in musb_rx_dma_iso_cppi41()
1465 void __iomem *epio = hw_ep->regs; in musb_rx_dma_iso_cppi41()
1470 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset + in musb_rx_dma_iso_cppi41()
1471 (u32)urb->transfer_dma; in musb_rx_dma_iso_cppi41()
1473 length = urb->iso_frame_desc[qh->iso_idx].length; in musb_rx_dma_iso_cppi41()
1477 musb_writew(hw_ep->regs, MUSB_RXCSR, val); in musb_rx_dma_iso_cppi41()
1479 return dma->channel_program(channel, qh->maxpacket, 0, in musb_rx_dma_iso_cppi41()
1496 submit_urb ->
1497 - if queue was empty, ProgramEndpoint
1498 - first IN token is sent out (by setting ReqPkt)
1499 LinuxIsr -> RxReady()
1501 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1502 | -> DMA Isr (transfer complete) -> RxReady()
1503 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1504 | - if urb not complete, send next IN token (ReqPkt)
1507 ---------------------------
1509 * Nuances of mode 1:
1514 * difficult. Hence mode 1 is not used.
1521 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1523 * - overflow (full, PLUS more bytes in the terminal packet)
1525 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1526 * thus be a great candidate for using mode 1 ... for all but the
1535 struct dma_channel *channel = hw_ep->rx_channel; in musb_rx_dma_inventra_cppi41()
1536 void __iomem *epio = hw_ep->regs; in musb_rx_dma_inventra_cppi41()
1541 pipe = urb->pipe; in musb_rx_dma_inventra_cppi41()
1546 d = urb->iso_frame_desc + qh->iso_idx; in musb_rx_dma_inventra_cppi41()
1547 d->actual_length = len; in musb_rx_dma_inventra_cppi41()
1550 * for iso_frame_desc->length in musb_rx_dma_inventra_cppi41()
1552 if (d->status != -EILSEQ && d->status != -EOVERFLOW) in musb_rx_dma_inventra_cppi41()
1553 d->status = 0; in musb_rx_dma_inventra_cppi41()
1555 if (++qh->iso_idx >= urb->number_of_packets) { in musb_rx_dma_inventra_cppi41()
1559 if (musb_dma_cppi41(hw_ep->musb)) in musb_rx_dma_inventra_cppi41()
1567 done = (urb->actual_length + len >= in musb_rx_dma_inventra_cppi41()
1568 urb->transfer_buffer_length in musb_rx_dma_inventra_cppi41()
1569 || channel->actual_len < qh->maxpacket in musb_rx_dma_inventra_cppi41()
1570 || channel->rx_packet_done); in musb_rx_dma_inventra_cppi41()
1583 /* Disadvantage of using mode 1:
1589 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1590 * to use the extra IN token to grab the last packet using mode 0, then
1593 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1595 * try to configure for mode 0 soon after the mode 1 transfer is
1606 struct musb *musb = hw_ep->musb; in musb_rx_dma_in_inventra_cppi41()
1607 void __iomem *epio = hw_ep->regs; in musb_rx_dma_in_inventra_cppi41()
1608 struct dma_channel *channel = hw_ep->rx_channel; in musb_rx_dma_in_inventra_cppi41()
1614 pipe = urb->pipe; in musb_rx_dma_in_inventra_cppi41()
1620 d = urb->iso_frame_desc + qh->iso_idx; in musb_rx_dma_in_inventra_cppi41()
1623 d_status = -EILSEQ; in musb_rx_dma_in_inventra_cppi41()
1624 urb->error_count++; in musb_rx_dma_in_inventra_cppi41()
1626 if (rx_count > d->length) { in musb_rx_dma_in_inventra_cppi41()
1628 d_status = -EOVERFLOW; in musb_rx_dma_in_inventra_cppi41()
1629 urb->error_count++; in musb_rx_dma_in_inventra_cppi41()
1632 rx_count, d->length); in musb_rx_dma_in_inventra_cppi41()
1634 length = d->length; in musb_rx_dma_in_inventra_cppi41()
1637 d->status = d_status; in musb_rx_dma_in_inventra_cppi41()
1638 buf = urb->transfer_dma + d->offset; in musb_rx_dma_in_inventra_cppi41()
1641 buf = urb->transfer_dma + urb->actual_length; in musb_rx_dma_in_inventra_cppi41()
1644 channel->desired_mode = 0; in musb_rx_dma_in_inventra_cppi41()
1646 /* because of the issue below, mode 1 will in musb_rx_dma_in_inventra_cppi41()
1649 if ((urb->transfer_flags & URB_SHORT_NOT_OK) in musb_rx_dma_in_inventra_cppi41()
1650 && (urb->transfer_buffer_length - urb->actual_length) in musb_rx_dma_in_inventra_cppi41()
1651 > qh->maxpacket) in musb_rx_dma_in_inventra_cppi41()
1652 channel->desired_mode = 1; in musb_rx_dma_in_inventra_cppi41()
1653 if (rx_count < hw_ep->max_packet_sz_rx) { in musb_rx_dma_in_inventra_cppi41()
1655 channel->desired_mode = 0; in musb_rx_dma_in_inventra_cppi41()
1657 length = urb->transfer_buffer_length; in musb_rx_dma_in_inventra_cppi41()
1661 /* See comments above on disadvantages of using mode 1 */ in musb_rx_dma_in_inventra_cppi41()
1665 if (channel->desired_mode == 0) in musb_rx_dma_in_inventra_cppi41()
1672 if (qh->hb_mult == 1) in musb_rx_dma_in_inventra_cppi41()
1681 done = dma->channel_program(channel, qh->maxpacket, in musb_rx_dma_in_inventra_cppi41()
1682 channel->desired_mode, in musb_rx_dma_in_inventra_cppi41()
1686 dma->channel_release(channel); in musb_rx_dma_in_inventra_cppi41()
1687 hw_ep->rx_channel = NULL; in musb_rx_dma_in_inventra_cppi41()
1721 * and high-bandwidth IN transfer cases.
1726 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_rx()
1727 struct dma_controller *c = musb->dma_controller; in musb_host_rx()
1728 void __iomem *epio = hw_ep->regs; in musb_host_rx()
1729 struct musb_qh *qh = hw_ep->in_qh; in musb_host_rx()
1731 void __iomem *mbase = musb->mregs; in musb_host_rx()
1742 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; in musb_host_rx()
1750 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least in musb_host_rx()
1768 status = -EPIPE; in musb_host_rx()
1771 dev_err(musb->controller, "ep%d RX three-strikes error", epnum); in musb_host_rx()
1774 * The three-strikes error could only happen when the USB in musb_host_rx()
1776 * off. So return the fatal error -ESHUTDOWN so hopefully the in musb_host_rx()
1779 status = -ESHUTDOWN; in musb_host_rx()
1787 if (USB_ENDPOINT_XFER_ISOC != qh->type) { in musb_host_rx()
1798 if (usb_pipebulk(urb->pipe) in musb_host_rx()
1799 && qh->mux == 1 in musb_host_rx()
1800 && !list_is_singular(&musb->in_bulk)) { in musb_host_rx()
1818 status = -EPROTO; in musb_host_rx()
1825 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_rx()
1826 musb->dma_controller->channel_abort(dma); in musb_host_rx()
1827 xfer_len = dma->actual_len; in musb_host_rx()
1846 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ in musb_host_rx()
1855 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_rx()
1856 musb->dma_controller->channel_abort(dma); in musb_host_rx()
1857 xfer_len = dma->actual_len; in musb_host_rx()
1871 xfer_len = dma->actual_len; in musb_host_rx()
1877 musb_writew(hw_ep->regs, MUSB_RXCSR, val); in musb_host_rx()
1882 musb_dbg(hw_ep->musb, in musb_host_rx()
1891 } else if (urb->status == -EINPROGRESS) { in musb_host_rx()
1894 status = -EPROTO; in musb_host_rx()
1910 musb_dbg(hw_ep->musb, in musb_host_rx()
1913 (unsigned long long) urb->transfer_dma in musb_host_rx()
1914 + urb->actual_length, in musb_host_rx()
1915 qh->offset, in musb_host_rx()
1916 urb->transfer_buffer_length); in musb_host_rx()
1922 dev_err(musb->controller, "error: rx_dma failed\n"); in musb_host_rx()
1929 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); in musb_host_rx()
1935 if (!urb->transfer_buffer) { in musb_host_rx()
1936 qh->use_sg = true; in musb_host_rx()
1937 sg_miter_start(&qh->sg_miter, urb->sg, 1, in musb_host_rx()
1941 if (qh->use_sg) { in musb_host_rx()
1942 if (!sg_miter_next(&qh->sg_miter)) { in musb_host_rx()
1943 dev_err(musb->controller, "error: sg list empty\n"); in musb_host_rx()
1944 sg_miter_stop(&qh->sg_miter); in musb_host_rx()
1945 status = -EINVAL; in musb_host_rx()
1949 urb->transfer_buffer = qh->sg_miter.addr; in musb_host_rx()
1950 received_len = urb->actual_length; in musb_host_rx()
1951 qh->offset = 0x0; in musb_host_rx()
1955 received_len = urb->actual_length - in musb_host_rx()
1957 qh->sg_miter.consumed = received_len; in musb_host_rx()
1958 sg_miter_stop(&qh->sg_miter); in musb_host_rx()
1968 urb->actual_length += xfer_len; in musb_host_rx()
1969 qh->offset += xfer_len; in musb_host_rx()
1971 if (qh->use_sg) { in musb_host_rx()
1972 qh->use_sg = false; in musb_host_rx()
1973 urb->transfer_buffer = NULL; in musb_host_rx()
1976 if (urb->status == -EINPROGRESS) in musb_host_rx()
1977 urb->status = status; in musb_host_rx()
1997 u8 toggle; in musb_schedule() local
2002 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { in musb_schedule()
2003 head = &musb->control; in musb_schedule()
2004 hw_ep = musb->control_ep; in musb_schedule()
2018 best_end = -1; in musb_schedule()
2020 for (epnum = 1, hw_ep = musb->endpoints + 1; in musb_schedule()
2021 epnum < musb->nr_endpoints; in musb_schedule()
2028 if (hw_ep == musb->bulk_ep) in musb_schedule()
2032 diff = hw_ep->max_packet_sz_rx; in musb_schedule()
2034 diff = hw_ep->max_packet_sz_tx; in musb_schedule()
2035 diff -= (qh->maxpacket * qh->hb_mult); in musb_schedule()
2043 * a zero toggle. If the BULK transfer starts on a 1 in musb_schedule()
2044 * toggle then this transfer will fail as the mentor in musb_schedule()
2045 * controller starts the Bulk transfer on a 0 toggle in musb_schedule()
2046 * irrespective of the programming of the toggle bits in musb_schedule()
2051 hw_ep = musb->endpoints + epnum; in musb_schedule()
2052 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); in musb_schedule()
2053 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) in musb_schedule()
2055 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && in musb_schedule()
2056 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) in musb_schedule()
2064 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { in musb_schedule()
2065 hw_ep = musb->bulk_ep; in musb_schedule()
2067 head = &musb->in_bulk; in musb_schedule()
2069 head = &musb->out_bulk; in musb_schedule()
2078 if (qh->dev) in musb_schedule()
2079 qh->intv_reg = in musb_schedule()
2080 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; in musb_schedule()
2083 dev_err(musb->controller, in musb_schedule()
2085 musb_ep_xfertype_string(qh->type), in musb_schedule()
2086 qh->hb_mult, qh->maxpacket); in musb_schedule()
2087 return -ENOSPC; in musb_schedule()
2091 qh->mux = 0; in musb_schedule()
2092 hw_ep = musb->endpoints + best_end; in musb_schedule()
2097 list_add_tail(&qh->ring, head); in musb_schedule()
2098 qh->mux = 1; in musb_schedule()
2100 qh->hw_ep = hw_ep; in musb_schedule()
2101 qh->hep->hcpriv = qh; in musb_schedule()
2114 struct usb_host_endpoint *hep = urb->ep; in musb_urb_enqueue()
2116 struct usb_endpoint_descriptor *epd = &hep->desc; in musb_urb_enqueue()
2122 if (!is_host_active(musb) || !musb->is_active) in musb_urb_enqueue()
2123 return -ENODEV; in musb_urb_enqueue()
2127 spin_lock_irqsave(&musb->lock, flags); in musb_urb_enqueue()
2129 qh = ret ? NULL : hep->hcpriv; in musb_urb_enqueue()
2131 urb->hcpriv = qh; in musb_urb_enqueue()
2132 spin_unlock_irqrestore(&musb->lock, flags); in musb_urb_enqueue()
2135 * hep->urb_list now ... so we're done, unless hep wasn't yet in musb_urb_enqueue()
2138 * REVISIT best to keep hep->hcpriv valid until the endpoint gets in musb_urb_enqueue()
2139 * disabled, testing for empty qh->ring and avoiding qh setup costs in musb_urb_enqueue()
2153 spin_lock_irqsave(&musb->lock, flags); in musb_urb_enqueue()
2155 spin_unlock_irqrestore(&musb->lock, flags); in musb_urb_enqueue()
2156 return -ENOMEM; in musb_urb_enqueue()
2159 qh->hep = hep; in musb_urb_enqueue()
2160 qh->dev = urb->dev; in musb_urb_enqueue()
2161 INIT_LIST_HEAD(&qh->ring); in musb_urb_enqueue()
2162 qh->is_ready = 1; in musb_urb_enqueue()
2164 qh->maxpacket = usb_endpoint_maxp(epd); in musb_urb_enqueue()
2165 qh->type = usb_endpoint_type(epd); in musb_urb_enqueue()
2171 qh->hb_mult = usb_endpoint_maxp_mult(epd); in musb_urb_enqueue()
2172 if (qh->hb_mult > 1) { in musb_urb_enqueue()
2173 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); in musb_urb_enqueue()
2176 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) in musb_urb_enqueue()
2177 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); in musb_urb_enqueue()
2179 dev_err(musb->controller, in musb_urb_enqueue()
2181 musb_ep_xfertype_string(qh->type), in musb_urb_enqueue()
2182 qh->hb_mult, qh->maxpacket & 0x7ff); in musb_urb_enqueue()
2183 ret = -EMSGSIZE; in musb_urb_enqueue()
2186 qh->maxpacket &= 0x7ff; in musb_urb_enqueue()
2189 qh->epnum = usb_endpoint_num(epd); in musb_urb_enqueue()
2191 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ in musb_urb_enqueue()
2192 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); in musb_urb_enqueue()
2195 type_reg = (qh->type << 4) | qh->epnum; in musb_urb_enqueue()
2196 switch (urb->dev->speed) { in musb_urb_enqueue()
2206 qh->type_reg = type_reg; in musb_urb_enqueue()
2209 switch (qh->type) { in musb_urb_enqueue()
2215 if (urb->dev->speed <= USB_SPEED_FULL) { in musb_urb_enqueue()
2216 interval = max_t(u8, epd->bInterval, 1); in musb_urb_enqueue()
2222 interval = min_t(u8, epd->bInterval, 16); in musb_urb_enqueue()
2229 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; in musb_urb_enqueue()
2241 qh->intv_reg = interval; in musb_urb_enqueue()
2244 if (musb->is_multipoint) { in musb_urb_enqueue()
2245 struct usb_device *parent = urb->dev->parent; in musb_urb_enqueue()
2247 if (parent != hcd->self.root_hub) { in musb_urb_enqueue()
2248 qh->h_addr_reg = (u8) parent->devnum; in musb_urb_enqueue()
2251 if (urb->dev->tt) { in musb_urb_enqueue()
2252 qh->h_port_reg = (u8) urb->dev->ttport; in musb_urb_enqueue()
2253 if (urb->dev->tt->hub) in musb_urb_enqueue()
2254 qh->h_addr_reg = in musb_urb_enqueue()
2255 (u8) urb->dev->tt->hub->devnum; in musb_urb_enqueue()
2256 if (urb->dev->tt->multi) in musb_urb_enqueue()
2257 qh->h_addr_reg |= 0x80; in musb_urb_enqueue()
2262 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. in musb_urb_enqueue()
2266 spin_lock_irqsave(&musb->lock, flags); in musb_urb_enqueue()
2267 if (hep->hcpriv || !next_urb(qh)) { in musb_urb_enqueue()
2276 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); in musb_urb_enqueue()
2279 urb->hcpriv = qh; in musb_urb_enqueue()
2280 /* FIXME set urb->start_frame for iso/intr, it's tested in in musb_urb_enqueue()
2284 spin_unlock_irqrestore(&musb->lock, flags); in musb_urb_enqueue()
2288 spin_lock_irqsave(&musb->lock, flags); in musb_urb_enqueue()
2290 spin_unlock_irqrestore(&musb->lock, flags); in musb_urb_enqueue()
2304 struct musb_hw_ep *ep = qh->hw_ep; in musb_cleanup_urb()
2305 struct musb *musb = ep->musb; in musb_cleanup_urb()
2306 void __iomem *epio = ep->regs; in musb_cleanup_urb()
2307 unsigned hw_end = ep->epnum; in musb_cleanup_urb()
2308 void __iomem *regs = ep->musb->mregs; in musb_cleanup_urb()
2309 int is_in = usb_pipein(urb->pipe); in musb_cleanup_urb()
2317 dma = is_in ? ep->rx_channel : ep->tx_channel; in musb_cleanup_urb()
2319 status = ep->musb->dma_controller->channel_abort(dma); in musb_cleanup_urb()
2320 musb_dbg(musb, "abort %cX%d DMA for urb %p --> %d", in musb_cleanup_urb()
2321 is_in ? 'R' : 'T', ep->epnum, in musb_cleanup_urb()
2323 urb->actual_length += dma->actual_len; in musb_cleanup_urb()
2328 if (ep->epnum && is_in) { in musb_cleanup_urb()
2329 /* giveback saves bulk toggle */ in musb_cleanup_urb()
2334 musb_platform_clear_ep_rxintr(musb, ep->epnum); in musb_cleanup_urb()
2335 } else if (ep->epnum) { in musb_cleanup_urb()
2353 musb_advance_schedule(ep->musb, urb, ep, is_in); in musb_cleanup_urb()
2362 int is_in = usb_pipein(urb->pipe); in musb_urb_dequeue()
2367 spin_lock_irqsave(&musb->lock, flags); in musb_urb_dequeue()
2372 qh = urb->hcpriv; in musb_urb_dequeue()
2382 * Otherwise abort current transfer, pending DMA, etc.; urb->status in musb_urb_dequeue()
2386 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) in musb_urb_dequeue()
2388 if (!qh->is_ready in musb_urb_dequeue()
2389 || urb->urb_list.prev != &qh->hep->urb_list in musb_urb_dequeue()
2390 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { in musb_urb_dequeue()
2391 int ready = qh->is_ready; in musb_urb_dequeue()
2393 qh->is_ready = 0; in musb_urb_dequeue()
2395 qh->is_ready = ready; in musb_urb_dequeue()
2400 if (ready && list_empty(&qh->hep->urb_list)) { in musb_urb_dequeue()
2401 qh->hep->hcpriv = NULL; in musb_urb_dequeue()
2402 list_del(&qh->ring); in musb_urb_dequeue()
2408 spin_unlock_irqrestore(&musb->lock, flags); in musb_urb_dequeue()
2416 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; in musb_h_disable()
2422 spin_lock_irqsave(&musb->lock, flags); in musb_h_disable()
2424 qh = hep->hcpriv; in musb_h_disable()
2428 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ in musb_h_disable()
2431 qh->is_ready = 0; in musb_h_disable()
2432 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { in musb_h_disable()
2436 if (!urb->unlinked) in musb_h_disable()
2437 urb->status = -ESHUTDOWN; in musb_h_disable()
2445 while (!list_empty(&hep->urb_list)) { in musb_h_disable()
2447 urb->status = -ESHUTDOWN; in musb_h_disable()
2448 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); in musb_h_disable()
2452 * other transfers, and since !qh->is_ready nothing in musb_h_disable()
2455 while (!list_empty(&hep->urb_list)) in musb_h_disable()
2456 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); in musb_h_disable()
2458 hep->hcpriv = NULL; in musb_h_disable()
2459 list_del(&qh->ring); in musb_h_disable()
2463 spin_unlock_irqrestore(&musb->lock, flags); in musb_h_disable()
2470 return musb_readw(musb->mregs, MUSB_FRAME); in musb_h_get_frame_number()
2480 hcd->state = HC_STATE_RUNNING; in musb_h_start()
2481 musb->port1_status = 0; in musb_h_start()
2488 hcd->state = HC_STATE_HALT; in musb_h_stop()
2504 switch (musb->xceiv->otg->state) { in musb_bus_suspend()
2512 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in musb_bus_suspend()
2514 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; in musb_bus_suspend()
2520 if (musb->is_active) { in musb_bus_suspend()
2522 usb_otg_state_string(musb->xceiv->otg->state)); in musb_bus_suspend()
2523 return -EBUSY; in musb_bus_suspend()
2532 if (musb->config && in musb_bus_resume()
2533 musb->config->host_port_deassert_reset_at_resume) in musb_bus_resume()
2555 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) in musb_free_temp_buffer()
2560 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, in musb_free_temp_buffer()
2564 if (usb_pipeisoc(urb->pipe)) in musb_free_temp_buffer()
2565 length = urb->transfer_buffer_length; in musb_free_temp_buffer()
2567 length = urb->actual_length; in musb_free_temp_buffer()
2569 memcpy(temp->old_xfer_buffer, temp->data, length); in musb_free_temp_buffer()
2571 urb->transfer_buffer = temp->old_xfer_buffer; in musb_free_temp_buffer()
2572 kfree(temp->kmalloc_ptr); in musb_free_temp_buffer()
2574 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; in musb_free_temp_buffer()
2584 if (urb->num_sgs || urb->sg || in musb_alloc_temp_buffer()
2585 urb->transfer_buffer_length == 0 || in musb_alloc_temp_buffer()
2586 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) in musb_alloc_temp_buffer()
2592 kmalloc_size = urb->transfer_buffer_length + in musb_alloc_temp_buffer()
2593 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; in musb_alloc_temp_buffer()
2597 return -ENOMEM; in musb_alloc_temp_buffer()
2603 temp->kmalloc_ptr = kmalloc_ptr; in musb_alloc_temp_buffer()
2604 temp->old_xfer_buffer = urb->transfer_buffer; in musb_alloc_temp_buffer()
2606 memcpy(temp->data, urb->transfer_buffer, in musb_alloc_temp_buffer()
2607 urb->transfer_buffer_length); in musb_alloc_temp_buffer()
2608 urb->transfer_buffer = temp->data; in musb_alloc_temp_buffer()
2610 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; in musb_alloc_temp_buffer()
2627 if (musb->hwvers < MUSB_HWVERS_1800) in musb_map_urb_for_dma()
2648 if (musb->hwvers < MUSB_HWVERS_1800) in musb_unmap_urb_for_dma()
2656 .description = "musb-hcd",
2689 struct device *dev = musb->controller; in musb_host_alloc()
2691 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ in musb_host_alloc()
2692 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); in musb_host_alloc()
2693 if (!musb->hcd) in musb_host_alloc()
2694 return -EINVAL; in musb_host_alloc()
2696 *musb->hcd->hcd_priv = (unsigned long) musb; in musb_host_alloc()
2697 musb->hcd->self.uses_pio_for_control = 1; in musb_host_alloc()
2698 musb->hcd->uses_new_polling = 1; in musb_host_alloc()
2699 musb->hcd->has_tt = 1; in musb_host_alloc()
2706 if (musb->port_mode == MUSB_PERIPHERAL) in musb_host_cleanup()
2708 usb_remove_hcd(musb->hcd); in musb_host_cleanup()
2713 usb_put_hcd(musb->hcd); in musb_host_free()
2719 struct usb_hcd *hcd = musb->hcd; in musb_host_setup()
2721 if (musb->port_mode == MUSB_HOST) { in musb_host_setup()
2723 musb->xceiv->otg->state = OTG_STATE_A_IDLE; in musb_host_setup()
2725 otg_set_host(musb->xceiv->otg, &hcd->self); in musb_host_setup()
2727 hcd->self.otg_port = 0; in musb_host_setup()
2728 musb->xceiv->otg->host = &hcd->self; in musb_host_setup()
2729 hcd->power_budget = 2 * (power_budget ? : 250); in musb_host_setup()
2730 hcd->skip_phy_initialization = 1; in musb_host_setup()
2736 device_wakeup_enable(hcd->self.controller); in musb_host_setup()
2742 usb_hcd_resume_root_hub(musb->hcd); in musb_host_resume_root_hub()
2748 if (musb->hcd->status_urb) in musb_host_poke_root_hub()
2749 usb_hcd_poll_rh_status(musb->hcd); in musb_host_poke_root_hub()
2751 usb_hcd_resume_root_hub(musb->hcd); in musb_host_poke_root_hub()