Lines Matching full:csr
90 u16 csr; in musb_h_tx_flush_fifo() local
93 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo()
96 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
114 "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_tx_flush_fifo()
115 ep->epnum, csr)) in musb_h_tx_flush_fifo()
124 u16 csr; in musb_h_ep0_flush_fifo() local
129 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()
133 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
137 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_ep0_flush_fifo()
138 ep->epnum, csr); in musb_h_ep0_flush_fifo()
384 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) in musb_h_flush_rxfifo() argument
390 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; in musb_h_flush_rxfifo()
391 csr &= ~(MUSB_RXCSR_H_REQPKT in musb_h_flush_rxfifo()
396 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
397 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
411 u16 csr; in musb_host_packet_rx() local
484 csr = musb_readw(epio, MUSB_RXCSR); in musb_host_packet_rx()
485 csr |= MUSB_RXCSR_H_WZC_BITS; in musb_host_packet_rx()
487 musb_h_flush_rxfifo(hw_ep, csr); in musb_host_packet_rx()
490 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); in musb_host_packet_rx()
492 csr |= MUSB_RXCSR_H_REQPKT; in musb_host_packet_rx()
493 musb_writew(epio, MUSB_RXCSR, csr); in musb_host_packet_rx()
500 * when we do, use tx/rx reinit routine and then construct a new CSR
511 u16 csr; in musb_rx_reinit() local
520 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
521 if (csr & MUSB_TXCSR_MODE) { in musb_rx_reinit()
523 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
525 csr | MUSB_TXCSR_FRCDATATOG); in musb_rx_reinit()
532 if (csr & MUSB_TXCSR_DMAMODE) in musb_rx_reinit()
538 csr = musb_readw(ep->regs, MUSB_RXCSR); in musb_rx_reinit()
539 if (csr & MUSB_RXCSR_RXPKTRDY) in musb_rx_reinit()
573 u16 csr; in musb_tx_dma_set_mode_mentor() local
578 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_set_mode_mentor()
581 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; in musb_tx_dma_set_mode_mentor()
594 csr |= MUSB_TXCSR_AUTOSET; in musb_tx_dma_set_mode_mentor()
597 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); in musb_tx_dma_set_mode_mentor()
598 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ in musb_tx_dma_set_mode_mentor()
601 musb_writew(epio, MUSB_TXCSR, csr); in musb_tx_dma_set_mode_mentor()
646 u16 csr; in musb_tx_dma_program() local
651 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_program()
652 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in musb_tx_dma_program()
653 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); in musb_tx_dma_program()
676 u16 csr; in musb_ep_program() local
690 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
691 csr &= ~MUSB_TXCSR_DMAENAB; in musb_ep_program()
692 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
715 u16 csr; in musb_ep_program() local
719 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
741 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT in musb_ep_program()
749 csr |= MUSB_TXCSR_MODE; in musb_ep_program()
752 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
754 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
756 csr &= ~MUSB_TXCSR_DMAMODE; in musb_ep_program()
757 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
758 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
834 u16 csr = 0; in musb_ep_program() local
838 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
841 csr |= MUSB_RXCSR_DISNYET; in musb_ep_program()
844 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
846 if (csr & (MUSB_RXCSR_RXPKTRDY in musb_ep_program()
849 ERR("broken !rx_reinit, ep%d csr %04x\n", in musb_ep_program()
850 hw_ep->epnum, csr); in musb_ep_program()
853 csr &= MUSB_RXCSR_DISNYET; in musb_ep_program()
864 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
865 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
880 csr |= MUSB_RXCSR_DMAENAB; in musb_ep_program()
883 csr |= MUSB_RXCSR_H_REQPKT; in musb_ep_program()
884 musb_dbg(musb, "RXCSR%d := %04x", epnum, csr); in musb_ep_program()
885 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
886 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
1051 u16 csr, len; in musb_h_ep0_irq() local
1064 csr = musb_readw(epio, MUSB_CSR0); in musb_h_ep0_irq()
1065 len = (csr & MUSB_CSR0_RXPKTRDY) in musb_h_ep0_irq()
1070 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
1079 if (csr & MUSB_CSR0_H_RXSTALL) { in musb_h_ep0_irq()
1083 } else if (csr & MUSB_CSR0_H_ERROR) { in musb_h_ep0_irq()
1084 musb_dbg(musb, "no response, csr0 %04x", csr); in musb_h_ep0_irq()
1087 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { in musb_h_ep0_irq()
1110 if (csr & MUSB_CSR0_H_REQPKT) { in musb_h_ep0_irq()
1111 csr &= ~MUSB_CSR0_H_REQPKT; in musb_h_ep0_irq()
1112 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1113 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; in musb_h_ep0_irq()
1114 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1138 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1144 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1147 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1151 csr |= MUSB_CSR0_H_DIS_PING; in musb_h_ep0_irq()
1156 musb_dbg(musb, "ep0 STATUS, csr %04x", csr); in musb_h_ep0_irq()
1159 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1210 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); in musb_host_tx()
1217 musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr, in musb_host_tx()
1286 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); in musb_host_tx()
1346 "DMA complete but FIFO not empty, CSR %04x", in musb_host_tx()
1754 musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d", in musb_host_rx()
1837 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); in musb_host_rx()
2311 u16 csr; in musb_cleanup_urb() local
2330 csr = musb_h_flush_rxfifo(ep, 0); in musb_cleanup_urb()
2337 csr = musb_readw(epio, MUSB_TXCSR); in musb_cleanup_urb()
2338 csr &= ~(MUSB_TXCSR_AUTOSET in musb_cleanup_urb()
2344 musb_writew(epio, MUSB_TXCSR, csr); in musb_cleanup_urb()
2346 musb_writew(epio, MUSB_TXCSR, csr); in musb_cleanup_urb()
2348 csr = musb_readw(epio, MUSB_TXCSR); in musb_cleanup_urb()