Lines Matching full:rx
25 * - Correct RX DMA generally forces the engine into irq-per-packet mode,
33 * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401
38 * evidently also directly update the RX and TX CSRs ... so audit all
85 /* zero out entire rx state RAM entry for the channel */
86 static void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx) in cppi_reset_rx() argument
88 musb_writel(&rx->rx_skipbytes, 0, 0); in cppi_reset_rx()
89 musb_writel(&rx->rx_head, 0, 0); in cppi_reset_rx()
90 musb_writel(&rx->rx_sop, 0, 0); in cppi_reset_rx()
91 musb_writel(&rx->rx_current, 0, 0); in cppi_reset_rx()
92 musb_writel(&rx->rx_buf_current, 0, 0); in cppi_reset_rx()
93 musb_writel(&rx->rx_len_len, 0, 0); in cppi_reset_rx()
94 musb_writel(&rx->rx_cnt_cnt, 0, 0); in cppi_reset_rx()
165 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { in cppi_controller_start()
166 controller->rx[i].transmit = false; in cppi_controller_start()
167 controller->rx[i].index = i; in cppi_controller_start()
173 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) in cppi_controller_start()
174 cppi_pool_init(controller, controller->rx + i); in cppi_controller_start()
179 /* initialise tx/rx channel head pointers to zero */ in cppi_controller_start()
190 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { in cppi_controller_start()
191 struct cppi_channel *rx_ch = controller->rx + i; in cppi_controller_start()
192 struct cppi_rx_stateram __iomem *rx; in cppi_controller_start() local
196 rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i); in cppi_controller_start()
197 rx_ch->state_ram = rx; in cppi_controller_start()
198 cppi_reset_rx(rx); in cppi_controller_start()
207 /* enable tx/rx CPPI control */ in cppi_controller_start()
211 /* disable RNDIS mode, also host rx RNDIS autorequest */ in cppi_controller_start()
237 musb_dbg(musb, "Tearing down RX and TX Channels"); in cppi_controller_stop()
243 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) in cppi_controller_stop()
244 cppi_pool_free(controller->rx + i); in cppi_controller_stop()
247 * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is in cppi_controller_stop()
250 /*disable tx/rx cppi */ in cppi_controller_stop()
307 if (index >= ARRAY_SIZE(controller->rx)) { in cppi_channel_allocate()
311 cppi_ch = controller->rx + index; in cppi_channel_allocate()
355 struct cppi_rx_stateram __iomem *rx = c->state_ram; in cppi_dump_rx() local
360 "RX DMA%d%s: %d left, csr %04x, " in cppi_dump_rx()
368 musb_readl(&rx->rx_skipbytes, 0), in cppi_dump_rx()
369 musb_readl(&rx->rx_head, 0), in cppi_dump_rx()
370 musb_readl(&rx->rx_sop, 0), in cppi_dump_rx()
371 musb_readl(&rx->rx_current, 0), in cppi_dump_rx()
373 musb_readl(&rx->rx_buf_current, 0), in cppi_dump_rx()
374 musb_readl(&rx->rx_len_len, 0), in cppi_dump_rx()
375 musb_readl(&rx->rx_cnt_cnt, 0), in cppi_dump_rx()
376 musb_readl(&rx->rx_complete, 0) in cppi_dump_rx()
438 static void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx) in cppi_dump_rxq() argument
442 cppi_dump_rx(level, rx, tag); in cppi_dump_rxq()
443 if (rx->last_processed) in cppi_dump_rxq()
444 cppi_dump_rxbd("last", rx->last_processed); in cppi_dump_rxq()
445 for (bd = rx->head; bd; bd = bd->next) in cppi_dump_rxq()
450 /* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX;
451 * so we won't ever use it (see "CPPI RX Woes" below).
453 static inline int cppi_autoreq_update(struct cppi_channel *rx, in cppi_autoreq_update() argument
464 val = tmp & ~((0x3) << (rx->index * 2)); in cppi_autoreq_update()
472 val |= ((0x3) << (rx->index * 2)); in cppi_autoreq_update()
476 val |= ((0x1) << (rx->index * 2)); in cppi_autoreq_update()
495 if (n_bds && rx->channel.actual_len) { in cppi_autoreq_update()
496 void __iomem *regs = rx->hw_ep->regs; in cppi_autoreq_update()
512 * - RX builds new queues each time, to help handle routine "early
526 * in the TX paths. (RX can't do this, see below.)
530 * "transparent" DMA model is always correct, even on the RX side.
536 * TX is a lot more reasonable than RX; it doesn't need to run in
613 /* FIXME use BD pool like RX side does, and just queue in cppi_next_tx_segment()
670 * CPPI RX Woes:
672 * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte
680 * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but
688 * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have
689 * converse problems: (b) is handled right, but (a) loses badly. CPPI RX
693 * are intended as outputs for RX queues, not inputs...)
709 * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic
731 * try rx rndis mode
743 MODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic");
749 * @rx: dma channel
754 * See above notes about why we can't use multi-BD RX queues except in
762 cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket) in cppi_next_rx_segment() argument
764 unsigned maxpacket = rx->maxpacket; in cppi_next_rx_segment()
765 dma_addr_t addr = rx->buf_dma + rx->offset; in cppi_next_rx_segment()
766 size_t length = rx->buf_len - rx->offset; in cppi_next_rx_segment()
772 struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram; in cppi_next_rx_segment()
809 n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds); in cppi_next_rx_segment()
811 cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis); in cppi_next_rx_segment()
815 musb_dbg(musb, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) " in cppi_next_rx_segment()
817 rx->index, maxpacket, in cppi_next_rx_segment()
823 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) in cppi_next_rx_segment()
826 rx->channel.actual_len, rx->buf_len); in cppi_next_rx_segment()
831 bd = cppi_bd_alloc(rx); in cppi_next_rx_segment()
832 rx->head = bd; in cppi_next_rx_segment()
839 bd = cppi_bd_alloc(rx); in cppi_next_rx_segment()
855 rx->offset += bd_len; in cppi_next_rx_segment()
866 WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds); in cppi_next_rx_segment()
869 WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds); in cppi_next_rx_segment()
874 bd = rx->head; in cppi_next_rx_segment()
875 rx->tail = tail; in cppi_next_rx_segment()
885 for (d = rx->head; d; d = d->next) in cppi_next_rx_segment()
889 tail = rx->last_processed; in cppi_next_rx_segment()
895 core_rxirq_enable(tibase, rx->index + 1); in cppi_next_rx_segment()
910 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) in cppi_next_rx_segment()
915 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), in cppi_next_rx_segment()
919 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), in cppi_next_rx_segment()
923 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) in cppi_next_rx_segment()
927 rx->index, i, n_bds); in cppi_next_rx_segment()
929 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), in cppi_next_rx_segment()
933 cppi_dump_rx(4, rx, "/S"); in cppi_next_rx_segment()
940 * @mode: For RX, 1 unless the usb protocol driver promised to treat
992 /* TX channel? or RX? */ in cppi_channel_program()
1003 struct cppi_channel *rx = &cppi->rx[ch]; in cppi_rx_scan() local
1004 struct cppi_rx_stateram __iomem *state = rx->state_ram; in cppi_rx_scan()
1006 struct cppi_descriptor *last = rx->last_processed; in cppi_rx_scan()
1011 void __iomem *regs = rx->hw_ep->regs; in cppi_rx_scan()
1014 cppi_dump_rx(6, rx, "/K"); in cppi_rx_scan()
1016 bd = last ? last->next : rx->head; in cppi_rx_scan()
1035 rx->channel.actual_len); in cppi_rx_scan()
1053 musb_dbg(musb, "rx short %d/%d (%d)", in cppi_rx_scan()
1055 rx->channel.actual_len); in cppi_rx_scan()
1074 rx->channel.actual_len += len; in cppi_rx_scan()
1076 cppi_bd_free(rx, last); in cppi_rx_scan()
1083 rx->last_processed = last; in cppi_rx_scan()
1089 if (safe2ack == 0 || safe2ack == rx->last_processed->dma) in cppi_rx_scan()
1092 cppi_bd_free(rx, last); in cppi_rx_scan()
1093 rx->last_processed = NULL; in cppi_rx_scan()
1098 WARN_ON(rx->head); in cppi_rx_scan()
1100 musb_ep_select(cppi->mregs, rx->index + 1); in cppi_rx_scan()
1104 rx->index, in cppi_rx_scan()
1105 rx->head, rx->tail, in cppi_rx_scan()
1106 rx->last_processed in cppi_rx_scan()
1108 rx->last_processed->dma in cppi_rx_scan()
1112 cppi_dump_rxq(4, "/what?", rx); in cppi_rx_scan()
1118 rx->head = bd; in cppi_rx_scan()
1123 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
1130 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
1133 rx->head = NULL; in cppi_rx_scan()
1134 rx->tail = NULL; in cppi_rx_scan()
1137 cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned"); in cppi_rx_scan()
1147 u32 rx, tx; in cppi_interrupt() local
1158 rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); in cppi_interrupt()
1160 if (!tx && !rx) { in cppi_interrupt()
1166 musb_dbg(musb, "CPPI IRQ Tx%x Rx%x", tx, rx); in cppi_interrupt()
1222 * REVISIT use the same ack strategy as rx in cppi_interrupt()
1258 /* Start processing the RX block */ in cppi_interrupt()
1259 for (index = 0; rx; rx = rx >> 1, index++) { in cppi_interrupt()
1261 if (rx & 1) { in cppi_interrupt()
1264 rx_ch = cppi->rx + index; in cppi_interrupt()
1389 /* from RX or TX fault irq handler */ in cppi_channel_abort()
1457 * as the RX side ... this does no cleanup at all! in cppi_channel_abort()
1460 } else /* RX */ { in cppi_channel_abort()
1466 * current RX DMA state iff any pending fifo transfer is done. in cppi_channel_abort()
1508 * RX channels to quiesce (how??) and then temporarily in cppi_channel_abort()