1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include	"xhci-ext-caps.h"
23 #include "pci-quirks.h"
31 /* Max number of USB devices for any host controller - limit in section 6.1 */
33 /* Section 5.3.3 - MaxPorts */
43  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
45  * @hcs_params1:	HCSPARAMS1 - Structural Parameters 1
46  * @hcs_params2:	HCSPARAMS2 - Structural Parameters 2
47  * @hcs_params3:	HCSPARAMS3 - Structural Parameters 3
48  * @hcc_params:		HCCPARAMS - Capability Parameters
49  * @db_off:		DBOFF - Doorbell array offset
50  * @run_regs_off:	RTSOFF - Runtime register space offset
62 	/* Reserved up to (CAPLENGTH - 0x1C) */
66 /* bits 7:0 - how long is the Capabilities register */
71 /* HCSPARAMS1 - hcs_params1 - bitmasks */
77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
80 /* HCSPARAMS2 - hcs_params2 - bitmasks */
87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91 /* HCSPARAMS3 - hcs_params3 - bitmasks */
97 /* HCCPARAMS - hcc_params - bitmasks */
98 /* true: HC can use 64-bit address pointers */
102 /* true: HC uses 64-byte Device Context structures
103  * FIXME 64-byte context structures aren't supported yet.
116 /* true: HC supports Stopped - Short Packet */
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
127 /* db_off bitmask - bits 0:1 reserved */
130 /* run_regs_off bitmask - bits 0:4 reserved */
133 /* HCCPARAMS2 - hcc_params2 - bitmasks */
158  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159  * @command:		USBCMD - xHC command register
160  * @status:		USBSTS - xHC status register
165  * @cmd_ring:		CRP - 64-bit Command Ring Pointer
166  * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
167  * @config_reg:		CONFIG - Configure Register
168  * @port_status_base:	PORTSCn - base address for Port Status and Control
173  * @port_power_base:	PORTPMSCn - base address for
175  * @port_link_base:	PORTLIn - base address for Port Link Info (current
187 	/* rsvd: offset 0x20-2F */
191 	/* rsvd: offset 0x3C-3FF */
198 	/* registers for ports 2-255 */
202 /* USBCMD - USB command - command bitmasks */
203 /* start/stop HC execution - do not write unless HC is halted*/
205 /* Reset HC - resets internal HC state machine and all registers (except
210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
215 /* light reset (port status stays unchanged) - reset completed when this is 0 */
220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
225  * disabled, or powered-off state.
235 /* IMAN - Interrupt Management Register */
239 /* USBSTS - USB status - status bitmasks */
240 /* HC not running - set to 1 when run/stop bit is cleared. */
244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
249 /* save state status - '1' means xHC is saving state */
251 /* restore state status - '1' means xHC is restoring state */
257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
262  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
277 /* stop ring immediately - abort the currently executing command */
282 /* Command Ring pointer - bit mask for the lower 32 bits. */
285 /* CONFIG - Configure Register - config_reg bitmasks */
286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
292 /* bits 10:31 - reserved and should be preserved */
294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
300 /* true: port has an over-current condition */
304 /* Port Link State - bits 5:8
326  * 0 - undefined speed - port hasn't be initialized by a reset yet
327  * 1 - full speed
328  * 2 - low speed
329  * 3 - high speed
330  * 4 - super speed
331  * 5-15 reserved
359 /* Port Link State Write Strobe - set this when changing link state */
371 /* true: over-current change */
373 /* true: reset change - 1 to 0 transition of PORT_RESET */
375 /* port link status change - set on some port link state transitions:
377  *  ------------------------------------------------------------------------------
378  *  - U3 to Resume			Wakeup signaling from a device
379  *  - Resume to Recovery to U0		USB 3.0 device resume
380  *  - Resume to U0			USB 2.0 device resume
381  *  - U3 to Recovery to U0		Software resume of USB 3.0 device complete
382  *  - U3 to U0				Software resume of USB 2.0 device complete
383  *  - U2 to U0				L1 resume of USB 2.1 device complete
384  *  - U0 to U0 (???)			L1 entry rejection by USB 2.1 device
385  *  - U0 to disabled			L1 entry error with USB 2.1 device
386  *  - Any state to inactive		Error on USB 3.0 port
389 /* port configure error change - port failed to configure its link partner */
395 /* Cold Attach Status - xHC can set this bit to report device attached during
404 /* wake on over-current (enable) */
407 /* true: device is non-removable - for USB 3.0 roothub emulation */
409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
412 /* We mark duplicate entries with -1 */
413 #define DUPLICATE_ENTRY ((u8)(-1))
415 /* Port Power Management Status and Control - port_power_base bitmasks */
470  * struct xhci_intr_reg - Interrupt Register Set
471  * @irq_pending:	IMAN - Interrupt Management Register.  Used to enable
473  * @irq_control:	IMOD - Interrupt Moderation Register.
479  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
509 /* Counter used to count down the time to the next interrupt - HW use only */
517 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
521 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
530  * 		MFINDEX - current microframe number
545  * Bits  0 -  7: Endpoint target
546  * Bits  8 - 15: RsvdZ
547  * Bits 16 - 31: Stream ID
564  * @port_info:		Port offset, count, and protocol-defined information.
613  * @dev_info:	Route string, device speed, hub info, and last valid endpoint
614  * @dev_info2:	Max exit latency for device number, root hub port number
618  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
619  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
632 /* Route String - 0:19 */
634 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
638 /* Is this LS/FS device connected through a HS hub? - bit 25 */
640 /* Set if the device is a hub - bit 26 */
642 /* Index of the last valid endpoint context in this device context - 27:31 */
645 #define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
650 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
652 /* Root hub port number that is needed to access the USB device */
655 /* Maximum number of ports under a hub device */
661  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
662  * The Slot ID of the hub that isolates the high speed signaling from
663  * this low or full-speed device.  '0' if attached to root hub port.
667  * The number of the downstream facing port of the high-speed hub
675 /* USB device address - assigned by the HC */
694  * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
702  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
703  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
711 	/* offset 0x14 - 0x1f reserved for HC internal use */
717  * Endpoint State - bits 0:2
718  * 0 - disabled
719  * 1 - running
720  * 2 - halted due to halt condition - ok to manipulate endpoint ring
721  * 3 - stopped
722  * 4 - TRB error
723  * 5-7 - reserved
731 #define GET_EP_CTX_STATE(ctx)	(le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
733 /* Mult - Max number of burtst within an interval, in EP companion desc. */
738 /* Interval - period between requests to an endpoint - 125u increments. */
752  * Force Event - generate transfer events for all TRBs for this endpoint
767 /* bit 7 is Host Initiate Disable - for disabling stream selection */
799 	(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
801 	(le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
804  * It's useful to pre-allocate these for commands that cannot fail due to
805  * out-of-memory errors, like freeing streams.
826 	/* 64-bit stream ring address, cycle state, and stream type */
828 	/* offset 0x14 - 0x1f reserved for HC internal use */
832 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
868  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
872 	/* ep_interval is zero-based */
874 	/* mult and num_packets are one-based */
921 /* Percentage of bus bandwidth reserved for non-periodic transfers */
949 	/* ----  Related to URB cancellation ---- */
1042  * If a high speed hub is attached to the roothub, each TT associated with that
1043  * hub is a separate bandwidth domain.  The interval information for the
1063  * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
1066 	/* 64-bit device addresses; we only write 32-bit addresses */
1071 /* TODO: write function to set the 64-bit device DMA address */
1079 	/* 64-bit buffer address, or immediate data */
1093 /* Completion Code - only applicable for some types of TRBs */
1191 		return "Stopped - Length Invalid";  in xhci_trb_comp_code_string()
1193 		return "Stopped - Short Packet";  in xhci_trb_comp_code_string()
1214 	/* 64-bit segment pointer*/
1233 /* Address device - disable SetAddress */
1236 /* Configure Endpoint - Deconfigure */
1239 /* Stop Ring - Transfer State Preserve */
1271 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1272 #define TRB_TO_EP_INDEX(p)		((((p) & (0x1f << 16)) >> 16) - 1)
1288 /* Port ID - bits 31:24 */
1294 /* transfer_len bitmasks - bits 0:16 */
1301 /* Interrupter Target - which MSI-X vector to target the completion event at */
1308 /* Cycle bit - indicates TRB ownership by HC or HCD */
1374 /* Transfer Ring No-op (not for the command ring) */
1403 /* Force Header Command - generate a transaction or link management packet */
1405 /* No-op Command - not for transfer rings */
1407 /* TRB IDs 24-31 reserved */
1421 /* Device Notification Event - device sent function wake notification */
1423 /* MFINDEX Wrap Event - microframe counter wrapped */
1425 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1427 /* Nec vendor-specific command completion event. */
1450 		return "No-Op";  in xhci_trb_type_string()
1480 		return "No-Op Command";  in xhci_trb_type_string()
1507 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1518  * since the command ring is 64-byte aligned.
1523 #define MAX_RSVD_CMD_TRBS	(TRBS_PER_SEGMENT - 3)
1530 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
1531 					(addr & (TRB_MAX_BUFF_SIZE - 1)))
1545 	/* Max packet sized bounce buffer for td-fragmant alignment */
1642 	/* 64-bit event ring segment address */
1652 	/* xhci->event_ring keeps track of segment dma addresses */
1705 	/* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1763 	/* Cached register copies of read-only HC data */
1787 	/* msi-x vectors */
1829 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1832  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1835  * they see this status (any time they drop and re-acquire xhci->lock).
1839  * There are no reports of xHCI host controllers that display this issue.
1911 	/* Indicates that omitting hcd is supported if root hub has no ports */
1931 	/* platform-specific data -- must come last */
1958 		primary_hcd = hcd->primary_hcd;  in hcd_to_xhci()
1960 	return (struct xhci_hcd *) (primary_hcd->hcd_priv);  in hcd_to_xhci()
1965 	return xhci->main_hcd;  in xhci_to_hcd()
1970 	if (xhci->shared_hcd)  in xhci_get_usb3_hcd()
1971 		return xhci->shared_hcd;  in xhci_get_usb3_hcd()
1973 	if (!xhci->usb2_rhub.num_ports)  in xhci_get_usb3_hcd()
1974 		return xhci->main_hcd;  in xhci_get_usb3_hcd()
1988 	return xhci->allow_single_roothub &&  in xhci_has_one_roothub()
1989 	       (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);  in xhci_has_one_roothub()
1993 	dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1995 	dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1997 	dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1999 	dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2001 	dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2006  * Some xHCI implementations may support 64-bit address pointers.  Registers
2007  * with 64-bit address pointers should be written to with dword accesses by
2009  * xHCI implementations that do not support 64-bit address pointers will ignore
2025 	return xhci->quirks & XHCI_LINK_TRB_QUIRK;  in xhci_link_trb_quirk()
2227 	return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,  in xhci_urb_to_transfer_ring()
2228 					xhci_get_endpoint_index(&urb->ep->desc),  in xhci_urb_to_transfer_ring()
2229 					urb->stream_id);  in xhci_urb_to_transfer_ring()
2239 	if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&  in xhci_urb_suitable_for_idt()
2240 	    usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
2241 	    urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
2242 	    !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&  in xhci_urb_suitable_for_idt()
2243 	    !urb->num_sgs)  in xhci_urb_suitable_for_idt()
2479 			"type '%s' -> raw %08x %08x %08x %08x",  in xhci_decode_trb()
2521 	u32 hub;  in xhci_decode_slot_context()  local
2526 	hub = info & DEV_HUB;  in xhci_decode_slot_context()
2534 				s = "full-speed";  in xhci_decode_slot_context()
2537 				s = "low-speed";  in xhci_decode_slot_context()
2540 				s = "high-speed";  in xhci_decode_slot_context()
2543 				s = "super-speed";  in xhci_decode_slot_context()
2546 				s = "super-speed plus";  in xhci_decode_slot_context()
2551 			mtt ? " multi-TT" : "",  in xhci_decode_slot_context()
2552 			hub ? " Hub" : "",  in xhci_decode_slot_context()
2608 		      portsc & PORT_POWER	? "Powered" : "Powered-off",  in xhci_decode_portsc()
2609 		      portsc & PORT_CONNECT	? "Connected" : "Not-connected",  in xhci_decode_portsc()
2617 		ret += sprintf(str + ret, "In-Reset ");  in xhci_decode_portsc()