Lines Matching +full:autosuspend +full:- +full:delay +full:- +full:ms
1 /* SPDX-License-Identifier: GPL-2.0 */
48 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
61 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
80 /* PCI Intel-specific resume-enable register */
97 /* When no queues need Full-Speed Bandwidth Reclamation,
98 * delay this long before turning FSBR off */
110 * To facilitate the strongest possible byte-order checking from "sparse"
127 * with each endpoint, and qh->element (updated by the HC) is either:
128 * - the next unprocessed TD in the endpoint's queue, or
129 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
133 * place. Then qh->element is UHCI_PTR_TERM.
135 * In the schedule, qh->link maintains a list of QHs seen by the HC:
136 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
138 * qh->node is the software equivalent of qh->link. The differences
139 * are that the software list is doubly-linked and QHs in the UNLINKING
167 /* Next urb->iso_frame_desc entry */
171 short phase; /* Between 0 and period-1 */
191 #define qh_element(qh) READ_ONCE((qh)->element)
194 cpu_to_hc32((uhci), (qh)->dma_handle))
217 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
222 TD_CTRL_ACTLEN_MASK) /* 1-based */
227 #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
232 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
235 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
252 * the hardware words are 16-byte aligned, and we can have any amount of
255 * td->link points to either another TD (not necessarily for the same urb or
279 READ_ONCE((td)->status))
281 #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
292 * Asynchronous QHs (low-speed control, full-speed control, and bulk)
293 * go onto the period-1 interrupt list, since they all get accessed on
306 * dev 5 low-speed control QH
310 * There is a special terminating QH used to keep full-speed bandwidth
311 * reclamation active when no full-speed control or bulk QHs are linked
335 #define SKEL_INDEX(exponent) (9 - exponent)
355 * when there are no devices attached we delay for 1 second in the
359 * driver learns to autosuspend.)
416 Resume-Detect interrupts
433 unsigned long port_c_suspend; /* Bit-arrays of ports */
439 int rh_numports; /* Number of root-hub ports */
463 return (struct uhci_hcd *) (hcd->hcd_priv); in hcd_to_uhci()
470 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
473 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
477 * Private per-URB data
499 return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed; in uhci_is_aspeed()
504 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
512 return inl(uhci->io_addr + reg); in uhci_readl()
517 outl(val, uhci->io_addr + reg); in uhci_writel()
522 return inw(uhci->io_addr + reg); in uhci_readw()
527 outw(val, uhci->io_addr + reg); in uhci_writew()
532 return inb(uhci->io_addr + reg); in uhci_readb()
537 outb(val, uhci->io_addr + reg); in uhci_writeb()
541 /* Support non-PCI host controllers */
543 /* Support PCI and non-PCI host controllers */
544 #define uhci_has_pci_registers(u) ((u)->io_addr != 0)
546 /* Support non-PCI host controllers only */
551 /* Support (non-PCI) big endian host controllers */
552 #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
590 return inl(uhci->io_addr + reg); in uhci_readl()
592 return readl(uhci->regs + uhci_aspeed_reg(reg)); in uhci_readl()
595 return readl_be(uhci->regs + reg); in uhci_readl()
598 return readl(uhci->regs + reg); in uhci_readl()
604 outl(val, uhci->io_addr + reg); in uhci_writel()
606 writel(val, uhci->regs + uhci_aspeed_reg(reg)); in uhci_writel()
609 writel_be(val, uhci->regs + reg); in uhci_writel()
612 writel(val, uhci->regs + reg); in uhci_writel()
618 return inw(uhci->io_addr + reg); in uhci_readw()
620 return readl(uhci->regs + uhci_aspeed_reg(reg)); in uhci_readw()
623 return readw_be(uhci->regs + reg); in uhci_readw()
626 return readw(uhci->regs + reg); in uhci_readw()
632 outw(val, uhci->io_addr + reg); in uhci_writew()
634 writel(val, uhci->regs + uhci_aspeed_reg(reg)); in uhci_writew()
637 writew_be(val, uhci->regs + reg); in uhci_writew()
640 writew(val, uhci->regs + reg); in uhci_writew()
646 return inb(uhci->io_addr + reg); in uhci_readb()
648 return readl(uhci->regs + uhci_aspeed_reg(reg)); in uhci_readb()
651 return readb_be(uhci->regs + reg); in uhci_readb()
654 return readb(uhci->regs + reg); in uhci_readb()
660 outb(val, uhci->io_addr + reg); in uhci_writeb()
662 writel(val, uhci->regs + uhci_aspeed_reg(reg)); in uhci_writeb()
665 writeb_be(val, uhci->regs + reg); in uhci_writeb()
668 writeb(val, uhci->regs + reg); in uhci_writeb()
675 * UHCI controllers accessed through PCI work normally (little-endian
676 * everywhere), so we don't bother supporting a BE-only mode.
679 #define uhci_big_endian_desc(u) ((u)->big_endian_desc)