9 /* definitions used for the EHCI driver */
92  * ehci-timer.c) in parallel with this list.
269 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)  in ehci_to_hcd()  argument
271 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);  in ehci_to_hcd()
280 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)  argument
283  * EHCI Specification 0.95 Section 3.5
291 	/* first part defined by EHCI spec */
292 	__hc32			hw_next;	/* see EHCI 3.5.1 */
293 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
294 	__hc32			hw_token;       /* see EHCI 3.5.3 */
309 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)  argument
310 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)  argument
311 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)  argument
313 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
324 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)  argument
331 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))  argument
337  * can be used on one system with SoC EHCI controller using big-endian
338  * descriptors as well as a normal little-endian PCI EHCI controller.
347 #define QH_NEXT(ehci, dma) \  argument
348 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
351 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */  argument
373  * EHCI Specification 0.95 Section 3.6
380 /* first part defined by EHCI spec */
382 	__hc32			hw_next;	/* see EHCI 3.6.1 */
383 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
391 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
397 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
471  * acts like a qh would, if EHCI had them for ISO.
506  * EHCI Specification 0.95 Section 3.3
512 	/* first part defined by EHCI spec */
513 	__hc32			hw_next;           /* see EHCI 3.3.1 */
514 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
522 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)  argument
524 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
544  * EHCI Specification 0.95 Section 3.4
550 	/* first part defined by EHCI spec */
552 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
553 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
554 	__hc32			hw_uframe;		/* EHCI table 3-10 */
555 	__hc32			hw_results;		/* EHCI table 3-11 */
567 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)  argument
569 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
570 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
587  * EHCI Specification 0.96 Section 3.7
637 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\  argument
638 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
640 #define ehci_prepare_ports_for_controller_resume(ehci)			\  argument
641 		ehci_adjust_port_wakeup_flags(ehci, false, false)
648  * Some EHCI controllers have a Transaction Translator built into the
658 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)  in ehci_port_speed()  argument
660 	if (ehci_is_TDI(ehci)) {  in ehci_port_speed()
661 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
678 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED  argument
741 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,  in ehci_readl()  argument
745 	return ehci_big_endian_mmio(ehci) ?  in ehci_readl()
765 static inline void ehci_writel(const struct ehci_hcd *ehci,  in ehci_writel()  argument
769 	ehci_big_endian_mmio(ehci) ?  in ehci_writel()
773 	if (ehci->imx28_write_fix)  in ehci_writel()
786 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
790 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
796 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
797 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
800 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
807  * The AMCC 440EPx not only implements its EHCI registers in big-endian
810  * EHCI controllers accessed through PCI work normally (little-endian
816 /* cpu to ehci */
817 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
819 	return ehci_big_endian_desc(ehci)  in cpu_to_hc32()
824 /* ehci to cpu */
825 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
827 	return ehci_big_endian_desc(ehci)  in hc32_to_cpu()
832 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
834 	return ehci_big_endian_desc(ehci)  in hc32_to_cpup()
841 /* cpu to ehci */
842 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
847 /* ehci to cpu */
848 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
853 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
862 #define ehci_dbg(ehci, fmt, args...) \  argument
863 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
864 #define ehci_err(ehci, fmt, args...) \  argument
865 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866 #define ehci_info(ehci, fmt, args...) \  argument
867 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868 #define ehci_warn(ehci, fmt, args...) \  argument
869 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
873 /* Declarations of things exported for use by ehci platform drivers */
885 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
887 extern int	ehci_reset(struct ehci_hcd *ehci);
891 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,