Lines Matching +full:1 +full:w

73 #define S3C2410_UDC_FUNCADDR_UPDATE	(1 << 7)
75 #define S3C2410_UDC_PWR_ISOUP		(1 << 7) /* R/W */
76 #define S3C2410_UDC_PWR_RESET		(1 << 3) /* R   */
77 #define S3C2410_UDC_PWR_RESUME		(1 << 2) /* R/W */
78 #define S3C2410_UDC_PWR_SUSPEND		(1 << 1) /* R   */
79 #define S3C2410_UDC_PWR_ENSUSPEND	(1 << 0) /* R/W */
83 #define S3C2410_UDC_INT_EP4		(1 << 4) /* R/W (clear only) */
84 #define S3C2410_UDC_INT_EP3		(1 << 3) /* R/W (clear only) */
85 #define S3C2410_UDC_INT_EP2		(1 << 2) /* R/W (clear only) */
86 #define S3C2410_UDC_INT_EP1		(1 << 1) /* R/W (clear only) */
87 #define S3C2410_UDC_INT_EP0		(1 << 0) /* R/W (clear only) */
89 #define S3C2410_UDC_USBINT_RESET	(1 << 2) /* R/W (clear only) */
90 #define S3C2410_UDC_USBINT_RESUME	(1 << 1) /* R/W (clear only) */
91 #define S3C2410_UDC_USBINT_SUSPEND	(1 << 0) /* R/W (clear only) */
93 #define S3C2410_UDC_INTE_EP4		(1 << 4) /* R/W */
94 #define S3C2410_UDC_INTE_EP3		(1 << 3) /* R/W */
95 #define S3C2410_UDC_INTE_EP2		(1 << 2) /* R/W */
96 #define S3C2410_UDC_INTE_EP1		(1 << 1) /* R/W */
97 #define S3C2410_UDC_INTE_EP0		(1 << 0) /* R/W */
99 #define S3C2410_UDC_USBINTE_RESET	(1 << 2) /* R/W */
100 #define S3C2410_UDC_USBINTE_SUSPEND	(1 << 0) /* R/W */
108 #define S3C2410_UDC_ICSR1_CLRDT		(1 << 6) /* R/W */
109 #define S3C2410_UDC_ICSR1_SENTSTL	(1 << 5) /* R/W (clear only) */
110 #define S3C2410_UDC_ICSR1_SENDSTL	(1 << 4) /* R/W */
111 #define S3C2410_UDC_ICSR1_FFLUSH	(1 << 3) /* W   (set only) */
112 #define S3C2410_UDC_ICSR1_UNDRUN	(1 << 2) /* R/W (clear only) */
113 #define S3C2410_UDC_ICSR1_PKTRDY	(1 << 0) /* R/W (set only) */
115 #define S3C2410_UDC_ICSR2_AUTOSET	(1 << 7) /* R/W */
116 #define S3C2410_UDC_ICSR2_ISO		(1 << 6) /* R/W */
117 #define S3C2410_UDC_ICSR2_MODEIN	(1 << 5) /* R/W */
118 #define S3C2410_UDC_ICSR2_DMAIEN	(1 << 4) /* R/W */
120 #define S3C2410_UDC_OCSR1_CLRDT		(1 << 7) /* R/W */
121 #define S3C2410_UDC_OCSR1_SENTSTL	(1 << 6) /* R/W (clear only) */
122 #define S3C2410_UDC_OCSR1_SENDSTL	(1 << 5) /* R/W */
123 #define S3C2410_UDC_OCSR1_FFLUSH	(1 << 4) /* R/W */
124 #define S3C2410_UDC_OCSR1_DERROR	(1 << 3) /* R   */
125 #define S3C2410_UDC_OCSR1_OVRRUN	(1 << 2) /* R/W (clear only) */
126 #define S3C2410_UDC_OCSR1_PKTRDY	(1 << 0) /* R/W (clear only) */
128 #define S3C2410_UDC_OCSR2_AUTOCLR	(1 << 7) /* R/W */
129 #define S3C2410_UDC_OCSR2_ISO		(1 << 6) /* R/W */
130 #define S3C2410_UDC_OCSR2_DMAIEN	(1 << 5) /* R/W */
132 #define S3C2410_UDC_EP0_CSR_OPKRDY	(1 << 0)
133 #define S3C2410_UDC_EP0_CSR_IPKRDY	(1 << 1)
134 #define S3C2410_UDC_EP0_CSR_SENTSTL	(1 << 2)
135 #define S3C2410_UDC_EP0_CSR_DE		(1 << 3)
136 #define S3C2410_UDC_EP0_CSR_SE		(1 << 4)
137 #define S3C2410_UDC_EP0_CSR_SENDSTL	(1 << 5)
138 #define S3C2410_UDC_EP0_CSR_SOPKTRDY	(1 << 6)
139 #define S3C2410_UDC_EP0_CSR_SSE		(1 << 7)
141 #define S3C2410_UDC_MAXP_8		(1 << 0)
142 #define S3C2410_UDC_MAXP_16		(1 << 1)
143 #define S3C2410_UDC_MAXP_32		(1 << 2)
144 #define S3C2410_UDC_MAXP_64		(1 << 3)