47 /* Cx configuration and FIFO Empty Status register(0x120) */
49 #define DCFESR_FIFO_EMPTY(fifo)	(1 << 8 << (fifo))  argument
76 #define DMISGR1_MF_IN_INT(fifo)	(1 << (16 + (fifo)))  argument
85 #define DMISGR1_MF_OUTSPK_INT(fifo)	(0x3 << (fifo) * 2)  argument
109 #define DISGR1_OUT_INT(fifo)	(1 << ((fifo) * 2))  argument
110 #define DISGR1_SPK_INT(fifo)	(1 << 1 << ((fifo) * 2))  argument
111 #define DISGR1_IN_INT(fifo)	(1 << 16 << (fifo))  argument
163 /* Device FIFO Map Register (0x1A8) */
165 #define FIFOMAP_DIROUT(fifo)	(0x0 << 4 << (fifo) * 8)  argument
166 #define FIFOMAP_DIRIN(fifo)	(0x1 << 4 << (fifo) * 8)  argument
167 #define FIFOMAP_BIDIR(fifo)	(0x2 << 4 << (fifo) * 8)  argument
168 #define FIFOMAP_NA(fifo)	(0x3 << 4 << (fifo) * 8)  argument
172 /* Device FIFO Confuguration Register (0x1AC) */
174 #define FIFOCF_TYPE(type, fifo)	((type) << (fifo) * 8)  argument
175 #define FIFOCF_BLK_SIN(fifo)	(0x0 << (fifo) * 8 << 2)  argument
176 #define FIFOCF_BLK_DUB(fifo)	(0x1 << (fifo) * 8 << 2)  argument
177 #define FIFOCF_BLK_TRI(fifo)	(0x2 << (fifo) * 8 << 2)  argument
178 #define FIFOCF_BLKSZ_512(fifo)	(0x0 << (fifo) * 8 << 4)  argument
179 #define FIFOCF_BLKSZ_1024(fifo)	(0x1 << (fifo) * 8 << 4)  argument
180 #define FIFOCF_FIFO_EN(fifo)	(0x1 << (fifo) * 8 << 5)  argument
182 /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
183 #define FOTG210_FIBCR(fifo)	(0x1B0 + (fifo) * 4)  argument
187 /* Device DMA Target FIFO Number Register (0x1C0) */
194 #define DMATFNR_ACC_FN(fifo)	(1 << (fifo))  argument