Lines Matching +full:0 +full:xc400
48 #define DWC3_EVENT_TYPE_MASK 0xfe
50 #define DWC3_EVENT_TYPE_DEV 0
54 #define DWC3_DEVICE_EVENT_DISCONNECT 0
67 #define DWC3_OTG_ROLE_IDLE 0
71 #define DWC3_GEVNTCOUNT_MASK 0xfffc
73 #define DWC3_GSNPSID_MASK 0xffff0000
74 #define DWC3_GSNPSREV_MASK 0xffff
78 #define DWC3_XHCI_REGS_START 0x0
79 #define DWC3_XHCI_REGS_END 0x7fff
80 #define DWC3_GLOBALS_REGS_START 0xc100
81 #define DWC3_GLOBALS_REGS_END 0xc6ff
82 #define DWC3_DEVICE_REGS_START 0xc700
83 #define DWC3_DEVICE_REGS_END 0xcbff
84 #define DWC3_OTG_REGS_START 0xcc00
85 #define DWC3_OTG_REGS_END 0xccff
88 #define DWC3_GSBUSCFG0 0xc100
89 #define DWC3_GSBUSCFG1 0xc104
90 #define DWC3_GTXTHRCFG 0xc108
91 #define DWC3_GRXTHRCFG 0xc10c
92 #define DWC3_GCTL 0xc110
93 #define DWC3_GEVTEN 0xc114
94 #define DWC3_GSTS 0xc118
95 #define DWC3_GUCTL1 0xc11c
96 #define DWC3_GSNPSID 0xc120
97 #define DWC3_GGPIO 0xc124
98 #define DWC3_GUID 0xc128
99 #define DWC3_GUCTL 0xc12c
100 #define DWC3_GBUSERRADDR0 0xc130
101 #define DWC3_GBUSERRADDR1 0xc134
102 #define DWC3_GPRTBIMAP0 0xc138
103 #define DWC3_GPRTBIMAP1 0xc13c
104 #define DWC3_GHWPARAMS0 0xc140
105 #define DWC3_GHWPARAMS1 0xc144
106 #define DWC3_GHWPARAMS2 0xc148
107 #define DWC3_GHWPARAMS3 0xc14c
108 #define DWC3_GHWPARAMS4 0xc150
109 #define DWC3_GHWPARAMS5 0xc154
110 #define DWC3_GHWPARAMS6 0xc158
111 #define DWC3_GHWPARAMS7 0xc15c
112 #define DWC3_GDBGFIFOSPACE 0xc160
113 #define DWC3_GDBGLTSSM 0xc164
114 #define DWC3_GDBGBMU 0xc16c
115 #define DWC3_GDBGLSPMUX 0xc170
116 #define DWC3_GDBGLSP 0xc174
117 #define DWC3_GDBGEPINFO0 0xc178
118 #define DWC3_GDBGEPINFO1 0xc17c
119 #define DWC3_GPRTBIMAP_HS0 0xc180
120 #define DWC3_GPRTBIMAP_HS1 0xc184
121 #define DWC3_GPRTBIMAP_FS0 0xc188
122 #define DWC3_GPRTBIMAP_FS1 0xc18c
123 #define DWC3_GUCTL2 0xc19c
125 #define DWC3_VER_NUMBER 0xc1a0
126 #define DWC3_VER_TYPE 0xc1a4
128 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
129 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
131 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
133 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
135 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
136 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
138 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
139 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
140 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
141 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
143 #define DWC3_GHWPARAMS8 0xc600
144 #define DWC3_GUCTL3 0xc60c
145 #define DWC3_GFLADJ 0xc630
146 #define DWC3_GHWPARAMS9 0xc6e0
149 #define DWC3_DCFG 0xc700
150 #define DWC3_DCTL 0xc704
151 #define DWC3_DEVTEN 0xc708
152 #define DWC3_DSTS 0xc70c
153 #define DWC3_DGCMDPAR 0xc710
154 #define DWC3_DGCMD 0xc714
155 #define DWC3_DALEPENA 0xc720
156 #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */
158 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
159 #define DWC3_DEPCMDPAR2 0x00
160 #define DWC3_DEPCMDPAR1 0x04
161 #define DWC3_DEPCMDPAR0 0x08
162 #define DWC3_DEPCMD 0x0c
164 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
167 #define DWC3_OCFG 0xcc00
168 #define DWC3_OCTL 0xcc04
169 #define DWC3_OEVT 0xcc08
170 #define DWC3_OEVTEN 0xcc0C
171 #define DWC3_OSTS 0xcc10
175 /* Global SoC Bus Configuration INCRx Register 0 */
183 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
184 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
188 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
189 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
190 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
193 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
194 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
195 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
197 #define DWC3_TXFIFO 0
208 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
209 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
213 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
214 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
217 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
219 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
220 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
223 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
224 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
227 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
229 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
230 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
237 #define DWC3_GCTL_CLK_BUS (0)
255 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
276 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
277 #define DWC3_GSTS_CURMOD_DEVICE 0
289 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
293 #define UTMI_PHYIF_8_BIT 0
302 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
322 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
323 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
324 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
327 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
328 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
332 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
335 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
336 #define DWC3_GHWPARAMS0_MODE_GADGET 0
339 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
340 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
341 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
342 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
343 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
347 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
356 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
360 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
365 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
369 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
381 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
384 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
385 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
388 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
393 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
400 #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
410 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
413 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
415 #define DWC3_DCFG_SPEED_MASK (7 << 0)
416 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
417 #define DWC3_DCFG_SUPERSPEED (4 << 0)
418 #define DWC3_DCFG_HIGHSPEED (0 << 0)
419 #define DWC3_DCFG_FULLSPEED BIT(0)
422 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
423 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
432 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
438 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
447 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
458 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
460 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
463 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
483 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
485 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
500 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
505 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
508 #define DWC3_DSTS_CONNECTSPD (7 << 0)
510 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
511 #define DWC3_DSTS_SUPERSPEED (4 << 0)
512 #define DWC3_DSTS_HIGHSPEED (0 << 0)
513 #define DWC3_DSTS_FULLSPEED BIT(0)
516 #define DWC3_DGCMD_SET_LMP 0x01
517 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
518 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
521 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
522 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
524 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
525 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
526 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
527 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
528 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
530 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
535 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
536 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
537 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
539 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
540 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
545 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
546 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
552 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
553 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
554 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
555 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
556 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
557 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
559 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
561 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
562 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
563 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
565 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
567 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
573 #define DWC3_DEPCMD_TYPE_CONTROL 0
579 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
580 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
581 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
589 #define DWC3_OCFG_SRPCAP BIT(0)
599 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
622 #define DWC3_OEVT_ERROR BIT(0)
649 #define DWC3_OSTS_CONIDSTS BIT(0)
674 #define DWC3_EVENT_PENDING BIT(0)
681 #define DWC3_EP_FLAG_STALLED BIT(0)
730 #define DWC3_EP_ENABLED BIT(0)
777 DWC3_PHY_UNKNOWN = 0,
783 DWC3_EP0_UNKNOWN = 0,
790 EP0_UNCONNECTED = 0,
798 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
799 DWC3_LINK_STATE_U1 = 0x01,
800 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
801 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
802 DWC3_LINK_STATE_SS_DIS = 0x04,
803 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
804 DWC3_LINK_STATE_SS_INACT = 0x06,
805 DWC3_LINK_STATE_POLL = 0x07,
806 DWC3_LINK_STATE_RECOV = 0x08,
807 DWC3_LINK_STATE_HRESET = 0x09,
808 DWC3_LINK_STATE_CMPLY = 0x0a,
809 DWC3_LINK_STATE_LPBK = 0x0b,
810 DWC3_LINK_STATE_RESET = 0x0e,
811 DWC3_LINK_STATE_RESUME = 0x0f,
812 DWC3_LINK_STATE_MASK = 0x0f,
816 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
818 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
819 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
821 #define DWC3_TRBSTS_OK 0
827 #define DWC3_TRB_CTRL_HWO BIT(0)
831 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
834 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
835 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
837 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
888 #define DWC3_MODE(n) ((n) & 0x7)
891 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
894 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
895 #define DWC3_NUM_EPS_MASK (0x3f << 12)
902 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
940 #define DWC3_REQUEST_STATUS_QUEUED 0
1064 * 0 - utmi_sleep_n
1107 * 0 - -6dB de-emphasis
1114 * increments or 0 to disable.
1198 #define DWC3_IP 0x5533
1199 #define DWC31_IP 0x3331
1200 #define DWC32_IP 0x3332
1204 #define DWC3_REVISION_ANY 0x0
1205 #define DWC3_REVISION_173A 0x5533173a
1206 #define DWC3_REVISION_175A 0x5533175a
1207 #define DWC3_REVISION_180A 0x5533180a
1208 #define DWC3_REVISION_183A 0x5533183a
1209 #define DWC3_REVISION_185A 0x5533185a
1210 #define DWC3_REVISION_187A 0x5533187a
1211 #define DWC3_REVISION_188A 0x5533188a
1212 #define DWC3_REVISION_190A 0x5533190a
1213 #define DWC3_REVISION_194A 0x5533194a
1214 #define DWC3_REVISION_200A 0x5533200a
1215 #define DWC3_REVISION_202A 0x5533202a
1216 #define DWC3_REVISION_210A 0x5533210a
1217 #define DWC3_REVISION_220A 0x5533220a
1218 #define DWC3_REVISION_230A 0x5533230a
1219 #define DWC3_REVISION_240A 0x5533240a
1220 #define DWC3_REVISION_250A 0x5533250a
1221 #define DWC3_REVISION_260A 0x5533260a
1222 #define DWC3_REVISION_270A 0x5533270a
1223 #define DWC3_REVISION_280A 0x5533280a
1224 #define DWC3_REVISION_290A 0x5533290a
1225 #define DWC3_REVISION_300A 0x5533300a
1226 #define DWC3_REVISION_310A 0x5533310a
1227 #define DWC3_REVISION_330A 0x5533330a
1229 #define DWC31_REVISION_ANY 0x0
1230 #define DWC31_REVISION_110A 0x3131302a
1231 #define DWC31_REVISION_120A 0x3132302a
1232 #define DWC31_REVISION_160A 0x3136302a
1233 #define DWC31_REVISION_170A 0x3137302a
1234 #define DWC31_REVISION_180A 0x3138302a
1235 #define DWC31_REVISION_190A 0x3139302a
1237 #define DWC32_REVISION_ANY 0x0
1238 #define DWC32_REVISION_100A 0x3130302a
1242 #define DWC31_VERSIONTYPE_ANY 0x0
1243 #define DWC31_VERSIONTYPE_EA01 0x65613031
1244 #define DWC31_VERSIONTYPE_EA02 0x65613032
1245 #define DWC31_VERSIONTYPE_EA03 0x65613033
1246 #define DWC31_VERSIONTYPE_EA04 0x65613034
1247 #define DWC31_VERSIONTYPE_EA05 0x65613035
1248 #define DWC31_VERSIONTYPE_EA06 0x65613036
1337 #define INCRX_BURST_MODE 0
1350 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1351 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1352 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1353 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1354 #define DWC3_DEPEVT_STREAMEVT 0x06
1355 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1362 * 0x00 - Reserved
1363 * 0x01 - XferComplete
1364 * 0x02 - XferInProgress
1365 * 0x03 - XferNotReady
1366 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1367 * 0x05 - Reserved
1368 * 0x06 - StreamEvt
1369 * 0x07 - EPCmdCmplt
1387 #define DEPEVT_STATUS_BUSERR BIT(0)
1398 #define DEPEVT_STREAM_PRIME 0xfffe
1399 #define DEPEVT_STREAM_NOSTREAM 0x0
1413 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1419 * @device_event: indicates it's a device event. Should read as 0x00
1421 * 0 - DisconnEvt
1450 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1494 #define DWC3_HAS_PERIPHERAL BIT(0)
1553 { return 0; } in dwc3_host_init()
1572 { return 0; } in dwc3_gadget_init()
1576 { return 0; } in dwc3_gadget_set_test_mode()
1578 { return 0; } in dwc3_gadget_get_link_state()
1581 { return 0; } in dwc3_gadget_set_link_state()
1585 { return 0; } in dwc3_send_gadget_ep_cmd()
1588 { return 0; } in dwc3_send_gadget_generic_command()
1602 { return 0; } in dwc3_drd_init()
1623 return 0; in dwc3_gadget_suspend()
1628 return 0; in dwc3_gadget_resume()
1641 { return 0; } in dwc3_ulpi_init()