Lines Matching +full:disable +full:- +full:hibernation +full:- +full:mode
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
15 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
17 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
18 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
19 p->max_packet_count = 511; in dwc2_set_bcm_params()
20 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
25 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
27 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
28 p->otg_caps.srp_support = false; in dwc2_set_his_params()
29 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
30 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
31 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
32 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
33 p->max_transfer_size = 65535; in dwc2_set_his_params()
34 p->max_packet_count = 511; in dwc2_set_his_params()
35 p->host_channels = 16; in dwc2_set_his_params()
36 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
37 p->phy_utmi_width = 8; in dwc2_set_his_params()
38 p->i2c_enable = false; in dwc2_set_his_params()
39 p->reload_ctl = false; in dwc2_set_his_params()
40 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
42 p->change_speed_quirk = true; in dwc2_set_his_params()
43 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
48 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_jz4775_params()
50 p->otg_caps.hnp_support = false; in dwc2_set_jz4775_params()
51 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_jz4775_params()
52 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_jz4775_params()
53 p->phy_utmi_width = 16; in dwc2_set_jz4775_params()
54 p->activate_ingenic_overcurrent_detection = in dwc2_set_jz4775_params()
55 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_jz4775_params()
60 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x1600_params()
62 p->otg_caps.hnp_support = false; in dwc2_set_x1600_params()
63 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x1600_params()
64 p->host_channels = 16; in dwc2_set_x1600_params()
65 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x1600_params()
66 p->phy_utmi_width = 16; in dwc2_set_x1600_params()
67 p->activate_ingenic_overcurrent_detection = in dwc2_set_x1600_params()
68 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x1600_params()
73 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x2000_params()
75 p->otg_caps.hnp_support = false; in dwc2_set_x2000_params()
76 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x2000_params()
77 p->host_rx_fifo_size = 1024; in dwc2_set_x2000_params()
78 p->host_nperio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
79 p->host_perio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
80 p->host_channels = 16; in dwc2_set_x2000_params()
81 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x2000_params()
82 p->phy_utmi_width = 16; in dwc2_set_x2000_params()
83 p->activate_ingenic_overcurrent_detection = in dwc2_set_x2000_params()
84 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x2000_params()
89 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params()
91 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
92 p->no_clock_gating = true; in dwc2_set_s3c6400_params()
93 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
98 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_socfpga_agilex_params()
100 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_socfpga_agilex_params()
101 p->no_clock_gating = true; in dwc2_set_socfpga_agilex_params()
106 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params()
108 p->otg_caps.hnp_support = false; in dwc2_set_rk_params()
109 p->otg_caps.srp_support = false; in dwc2_set_rk_params()
110 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
111 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
112 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
113 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
115 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
120 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_params()
122 p->otg_caps.hnp_support = false; in dwc2_set_ltq_params()
123 p->otg_caps.srp_support = false; in dwc2_set_ltq_params()
124 p->host_rx_fifo_size = 288; in dwc2_set_ltq_params()
125 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_params()
126 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_params()
127 p->max_transfer_size = 65535; in dwc2_set_ltq_params()
128 p->max_packet_count = 511; in dwc2_set_ltq_params()
129 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_params()
135 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params()
137 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_params()
138 p->otg_caps.srp_support = false; in dwc2_set_amlogic_params()
139 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
140 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
141 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
142 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
143 p->host_channels = 16; in dwc2_set_amlogic_params()
144 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
145 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
147 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
152 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params()
154 p->lpm = false; in dwc2_set_amlogic_g12a_params()
155 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
156 p->besl = false; in dwc2_set_amlogic_g12a_params()
157 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
162 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params()
164 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
169 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params()
171 p->otg_caps.hnp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
172 p->otg_caps.srp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
173 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
174 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
175 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
176 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
177 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
178 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
179 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
180 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
185 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params()
187 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
188 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
189 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
194 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params()
196 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_fsotg_params()
197 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_fsotg_params()
198 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_fsotg_params()
199 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
200 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
201 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
202 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
203 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
204 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
205 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
206 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
207 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
208 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_fsotg_params()
209 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
210 p->host_support_fs_ls_low_power = true; in dwc2_set_stm32mp15_fsotg_params()
211 p->host_ls_low_power_phy_clk = true; in dwc2_set_stm32mp15_fsotg_params()
216 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params()
218 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_hsotg_params()
219 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_hsotg_params()
220 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_hsotg_params()
221 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
222 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
223 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
224 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
225 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_hsotg_params()
226 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
227 p->lpm = false; in dwc2_set_stm32mp15_hsotg_params()
228 p->lpm_clock_gating = false; in dwc2_set_stm32mp15_hsotg_params()
229 p->besl = false; in dwc2_set_stm32mp15_hsotg_params()
230 p->hird_threshold_en = false; in dwc2_set_stm32mp15_hsotg_params()
234 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
235 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
236 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
237 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
238 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
239 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
240 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
241 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
242 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
243 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
244 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
245 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
247 { .compatible = "samsung,s3c6400-hsotg",
249 { .compatible = "amlogic,meson8-usb",
251 { .compatible = "amlogic,meson8b-usb",
253 { .compatible = "amlogic,meson-gxbb-usb",
255 { .compatible = "amlogic,meson-g12a-usb",
257 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
258 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
259 { .compatible = "st,stm32f4x9-fsotg",
261 { .compatible = "st,stm32f4x9-hsotg" },
262 { .compatible = "st,stm32f7-hsotg",
264 { .compatible = "st,stm32mp15-fsotg",
266 { .compatible = "st,stm32mp15-hsotg",
268 { .compatible = "intel,socfpga-agilex-hsotg",
282 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
284 hsotg->params.otg_caps.hnp_support = true; in dwc2_set_param_otg_cap()
285 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
290 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
291 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
294 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
295 hsotg->params.otg_caps.srp_support = false; in dwc2_set_param_otg_cap()
303 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
315 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_param_phy_type()
317 hsotg->params.phy_type = val; in dwc2_set_param_phy_type()
324 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
333 hsotg->params.speed = val; in dwc2_set_param_speed()
340 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
343 if (hsotg->phy) { in dwc2_set_param_phy_utmi_width()
346 * width is 8-bit and set the phyif appropriately. in dwc2_set_param_phy_utmi_width()
348 if (phy_get_bus_width(hsotg->phy) == 8) in dwc2_set_param_phy_utmi_width()
352 hsotg->params.phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
357 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes()
364 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
367 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
374 if (hsotg->hw_params.hibernation) in dwc2_set_param_power_down()
376 else if (hsotg->hw_params.power_optimized) in dwc2_set_param_power_down()
381 hsotg->params.power_down = val; in dwc2_set_param_power_down()
386 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm()
388 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
389 if (p->lpm) { in dwc2_set_param_lpm()
390 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
391 p->besl = true; in dwc2_set_param_lpm()
392 p->hird_threshold_en = true; in dwc2_set_param_lpm()
393 p->hird_threshold = 4; in dwc2_set_param_lpm()
395 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
396 p->besl = false; in dwc2_set_param_lpm()
397 p->hird_threshold_en = false; in dwc2_set_param_lpm()
402 * dwc2_set_default_params() - Set all core parameters to their
403 * auto-detected default values.
410 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_set_default_params()
411 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params()
412 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_set_default_params()
420 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
421 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
423 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
424 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
425 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
426 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
427 p->ulpi_fs_ls = false; in dwc2_set_default_params()
428 p->ts_dline = false; in dwc2_set_default_params()
429 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
430 p->uframe_sched = true; in dwc2_set_default_params()
431 p->external_id_pin_ctl = false; in dwc2_set_default_params()
432 p->ipg_isoc_en = false; in dwc2_set_default_params()
433 p->service_interval = false; in dwc2_set_default_params()
434 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
435 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
436 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
437 p->ref_clk_per = 33333; in dwc2_set_default_params()
438 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
440 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_set_default_params()
441 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
442 p->host_dma = dma_capable; in dwc2_set_default_params()
443 p->dma_desc_enable = false; in dwc2_set_default_params()
444 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
445 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
446 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
447 p->host_channels = hw->host_channels; in dwc2_set_default_params()
448 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
449 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
450 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
453 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_set_default_params()
454 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
455 p->g_dma = dma_capable; in dwc2_set_default_params()
456 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
461 * gadget driver. These defaults have been hard-coded in dwc2_set_default_params()
464 * auto-detect if the hardware does not support the in dwc2_set_default_params()
467 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
468 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
474 * dwc2_get_device_properties() - Read in device properties.
482 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties()
485 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_get_device_properties()
486 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_get_device_properties()
487 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", in dwc2_get_device_properties()
488 &p->g_rx_fifo_size); in dwc2_get_device_properties()
490 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", in dwc2_get_device_properties()
491 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
493 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); in dwc2_get_device_properties()
496 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
497 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
498 device_property_read_u32_array(hsotg->dev, in dwc2_get_device_properties()
499 "g-tx-fifo-size", in dwc2_get_device_properties()
500 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
504 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); in dwc2_get_device_properties()
507 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) in dwc2_get_device_properties()
508 p->oc_disable = true; in dwc2_get_device_properties()
515 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
517 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_check_param_otg_cap()
519 } else if (!hsotg->params.otg_caps.hnp_support) { in dwc2_check_param_otg_cap()
521 if (hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
522 switch (hsotg->hw_params.op_mode) { in dwc2_check_param_otg_cap()
548 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_check_param_phy_type()
549 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_check_param_phy_type()
551 switch (hsotg->params.phy_type) { in dwc2_check_param_phy_type()
577 int phy_type = hsotg->params.phy_type; in dwc2_check_param_speed()
578 int speed = hsotg->params.speed; in dwc2_check_param_speed()
582 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && in dwc2_check_param_speed()
601 int param = hsotg->params.phy_utmi_width; in dwc2_check_param_phy_utmi_width()
602 int width = hsotg->hw_params.utmi_phy_data_width; in dwc2_check_param_phy_utmi_width()
622 int param = hsotg->params.power_down; in dwc2_check_param_power_down()
628 if (hsotg->hw_params.power_optimized) in dwc2_check_param_power_down()
630 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
635 if (hsotg->hw_params.hibernation) in dwc2_check_param_power_down()
637 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
638 "Hibernation isn't supported by HW\n"); in dwc2_check_param_power_down()
642 dev_err(hsotg->dev, in dwc2_check_param_power_down()
649 hsotg->params.power_down = param; in dwc2_check_param_power_down()
661 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; in dwc2_check_param_tx_fifo_sizes()
664 total += hsotg->params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
667 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", in dwc2_check_param_tx_fifo_sizes()
673 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
675 if (hsotg->params.g_tx_fifo_size[fifo] < min || in dwc2_check_param_tx_fifo_sizes()
676 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { in dwc2_check_param_tx_fifo_sizes()
677 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", in dwc2_check_param_tx_fifo_sizes()
679 hsotg->params.g_tx_fifo_size[fifo]); in dwc2_check_param_tx_fifo_sizes()
680 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; in dwc2_check_param_tx_fifo_sizes()
686 if ((int)(hsotg->params._param) < (_min) || \
687 (hsotg->params._param) > (_max)) { \
688 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
689 __func__, #_param, hsotg->params._param); \
690 hsotg->params._param = (_def); \
695 if (hsotg->params._param && !(_check)) { \
696 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
697 __func__, #_param, hsotg->params._param); \
698 hsotg->params._param = false; \
704 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_check_params()
705 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params()
706 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_check_params()
713 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); in dwc2_check_params()
714 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); in dwc2_check_params()
715 CHECK_BOOL(i2c_enable, hw->i2c_enable); in dwc2_check_params()
716 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); in dwc2_check_params()
717 CHECK_BOOL(acg_enable, hw->acg_enable); in dwc2_check_params()
718 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); in dwc2_check_params()
719 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); in dwc2_check_params()
720 CHECK_BOOL(lpm, hw->lpm_mode); in dwc2_check_params()
721 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); in dwc2_check_params()
722 CHECK_BOOL(besl, hsotg->params.lpm); in dwc2_check_params()
723 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); in dwc2_check_params()
724 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); in dwc2_check_params()
725 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); in dwc2_check_params()
726 CHECK_BOOL(service_interval, hw->service_interval_mode); in dwc2_check_params()
728 15, hw->max_packet_count, in dwc2_check_params()
729 hw->max_packet_count); in dwc2_check_params()
731 2047, hw->max_transfer_size, in dwc2_check_params()
732 hw->max_transfer_size); in dwc2_check_params()
734 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_check_params()
735 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
737 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
738 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
740 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
742 1, hw->host_channels, in dwc2_check_params()
743 hw->host_channels); in dwc2_check_params()
745 16, hw->rx_fifo_size, in dwc2_check_params()
746 hw->rx_fifo_size); in dwc2_check_params()
748 16, hw->host_nperio_tx_fifo_size, in dwc2_check_params()
749 hw->host_nperio_tx_fifo_size); in dwc2_check_params()
751 16, hw->host_perio_tx_fifo_size, in dwc2_check_params()
752 hw->host_perio_tx_fifo_size); in dwc2_check_params()
755 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_check_params()
756 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
758 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()
760 16, hw->rx_fifo_size, in dwc2_check_params()
761 hw->rx_fifo_size); in dwc2_check_params()
763 16, hw->dev_nperio_tx_fifo_size, in dwc2_check_params()
764 hw->dev_nperio_tx_fifo_size); in dwc2_check_params()
770 * Gets host hardware parameters. Forces host mode if not currently in
771 * host mode. Should be called immediately after a core soft reset in
776 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_host_hwparams()
780 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) in dwc2_get_host_hwparams()
788 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
790 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
795 * Gets device hardware parameters. Forces device mode if not
796 * currently in device mode. Should be called immediately after a core
801 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_dev_hwparams()
805 if (hsotg->dr_mode == USB_DR_MODE_HOST) in dwc2_get_dev_hwparams()
815 hw->g_tx_fifo_size[fifo] = in dwc2_get_dev_hwparams()
820 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_dev_hwparams()
825 * dwc2_get_hwparams() - During device initialization, read various hardware
833 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
845 hw->dev_ep_dirs = hwcfg1; in dwc2_get_hwparams()
848 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> in dwc2_get_hwparams()
850 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> in dwc2_get_hwparams()
852 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); in dwc2_get_hwparams()
853 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> in dwc2_get_hwparams()
855 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
857 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
859 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> in dwc2_get_hwparams()
861 hw->nperio_tx_q_depth = in dwc2_get_hwparams()
864 hw->host_perio_tx_q_depth = in dwc2_get_hwparams()
867 hw->dev_token_q_depth = in dwc2_get_hwparams()
874 hw->max_transfer_size = (1 << (width + 11)) - 1; in dwc2_get_hwparams()
877 hw->max_packet_count = (1 << (width + 4)) - 1; in dwc2_get_hwparams()
878 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); in dwc2_get_hwparams()
879 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> in dwc2_get_hwparams()
881 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); in dwc2_get_hwparams()
884 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); in dwc2_get_hwparams()
885 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> in dwc2_get_hwparams()
887 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> in dwc2_get_hwparams()
889 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); in dwc2_get_hwparams()
890 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); in dwc2_get_hwparams()
891 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); in dwc2_get_hwparams()
892 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> in dwc2_get_hwparams()
894 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); in dwc2_get_hwparams()
895 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); in dwc2_get_hwparams()
896 hw->service_interval_mode = !!(hwcfg4 & in dwc2_get_hwparams()
900 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> in dwc2_get_hwparams()
904 * requires the controller to be in host mode. The mode will in dwc2_get_hwparams()
923 match = of_match_device(dwc2_of_match_table, hsotg->dev); in dwc2_init_params()
924 if (match && match->data) { in dwc2_init_params()
925 set_params = match->data; in dwc2_init_params()
930 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); in dwc2_init_params()
931 if (amatch && amatch->driver_data) { in dwc2_init_params()
932 set_params = (set_params_cb)amatch->driver_data; in dwc2_init_params()