Lines Matching +full:disable +full:- +full:hibernation +full:- +full:mode
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
17 #include <linux/dma-mapping.h>
37 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
55 if (!hsotg->params.host_dma) in dwc2_enable_common_interrupts()
57 if (!hsotg->params.external_id_pin_ctl) in dwc2_enable_common_interrupts()
63 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) in dwc2_enable_common_interrupts()
73 switch (hsotg->hw_params.arch) { in dwc2_gahbcfg_init()
75 dev_err(hsotg->dev, "External DMA Mode not supported\n"); in dwc2_gahbcfg_init()
76 return -EINVAL; in dwc2_gahbcfg_init()
79 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); in dwc2_gahbcfg_init()
80 if (hsotg->params.ahbcfg != -1) { in dwc2_gahbcfg_init()
82 ahbcfg |= hsotg->params.ahbcfg & in dwc2_gahbcfg_init()
89 dev_dbg(hsotg->dev, "Slave Only Mode\n"); in dwc2_gahbcfg_init()
93 if (hsotg->params.host_dma) in dwc2_gahbcfg_init()
96 hsotg->params.dma_desc_enable = false; in dwc2_gahbcfg_init()
110 switch (hsotg->hw_params.op_mode) { in dwc2_gusbcfg_init()
112 if (hsotg->params.otg_caps.hnp_support && in dwc2_gusbcfg_init()
113 hsotg->params.otg_caps.srp_support) in dwc2_gusbcfg_init()
120 if (hsotg->params.otg_caps.srp_support) in dwc2_gusbcfg_init()
136 if (hsotg->vbus_supply) in dwc2_vbus_supply_init()
137 return regulator_enable(hsotg->vbus_supply); in dwc2_vbus_supply_init()
144 if (hsotg->vbus_supply) in dwc2_vbus_supply_exit()
145 return regulator_disable(hsotg->vbus_supply); in dwc2_vbus_supply_exit()
151 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
159 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_enable_host_interrupts()
161 /* Disable all interrupts */ in dwc2_enable_host_interrupts()
168 /* Enable host mode interrupts without disturbing common interrupts */ in dwc2_enable_host_interrupts()
175 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
183 /* Disable host mode interrupts without disturbing common interrupts */ in dwc2_disable_host_interrupts()
190 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
198 struct dwc2_core_params *params = &hsotg->params; in dwc2_calculate_dynamic_fifo()
199 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_calculate_dynamic_fifo()
202 total_fifo_size = hw->total_fifo_size; in dwc2_calculate_dynamic_fifo()
203 rxfsiz = params->host_rx_fifo_size; in dwc2_calculate_dynamic_fifo()
204 nptxfsiz = params->host_nperio_tx_fifo_size; in dwc2_calculate_dynamic_fifo()
205 ptxfsiz = params->host_perio_tx_fifo_size; in dwc2_calculate_dynamic_fifo()
211 * non-periodic as 512. in dwc2_calculate_dynamic_fifo()
215 * For Buffer DMA mode/Scatter Gather DMA mode in dwc2_calculate_dynamic_fifo()
220 rxfsiz = 516 + hw->host_channels; in dwc2_calculate_dynamic_fifo()
223 * min non-periodic tx fifo depth in dwc2_calculate_dynamic_fifo()
224 * 2 * (largest non-periodic USB packet used / 4) in dwc2_calculate_dynamic_fifo()
236 params->host_rx_fifo_size = rxfsiz; in dwc2_calculate_dynamic_fifo()
237 params->host_nperio_tx_fifo_size = nptxfsiz; in dwc2_calculate_dynamic_fifo()
238 params->host_perio_tx_fifo_size = ptxfsiz; in dwc2_calculate_dynamic_fifo()
252 dev_err(hsotg->dev, "invalid fifo sizes\n"); in dwc2_calculate_dynamic_fifo()
257 struct dwc2_core_params *params = &hsotg->params; in dwc2_config_fifos()
260 if (!params->enable_dynamic_fifo) in dwc2_config_fifos()
267 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); in dwc2_config_fifos()
269 grxfsiz |= params->host_rx_fifo_size << in dwc2_config_fifos()
272 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", in dwc2_config_fifos()
275 /* Non-periodic Tx FIFO */ in dwc2_config_fifos()
276 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", in dwc2_config_fifos()
278 nptxfsiz = params->host_nperio_tx_fifo_size << in dwc2_config_fifos()
280 nptxfsiz |= params->host_rx_fifo_size << in dwc2_config_fifos()
283 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", in dwc2_config_fifos()
287 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", in dwc2_config_fifos()
289 hptxfsiz = params->host_perio_tx_fifo_size << in dwc2_config_fifos()
291 hptxfsiz |= (params->host_rx_fifo_size + in dwc2_config_fifos()
292 params->host_nperio_tx_fifo_size) << in dwc2_config_fifos()
295 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", in dwc2_config_fifos()
298 if (hsotg->params.en_multiple_tx_fifo && in dwc2_config_fifos()
299 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { in dwc2_config_fifos()
302 * Global DFIFOCFG calculation for Host mode - in dwc2_config_fifos()
307 dfifocfg |= (params->host_rx_fifo_size + in dwc2_config_fifos()
308 params->host_nperio_tx_fifo_size + in dwc2_config_fifos()
309 params->host_perio_tx_fifo_size) << in dwc2_config_fifos()
317 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
338 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == in dwc2_calc_frame_interval()
351 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) in dwc2_calc_frame_interval()
354 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) in dwc2_calc_frame_interval()
359 return 125 * clock - 1; in dwc2_calc_frame_interval()
362 return 1000 * clock - 1; in dwc2_calc_frame_interval()
366 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
385 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); in dwc2_read_packet()
392 * dwc2_dump_channel_info() - Prints the state of a host channel
406 int num_channels = hsotg->params.host_channels; in dwc2_dump_channel_info()
417 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_dump_channel_info()
418 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); in dwc2_dump_channel_info()
419 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num)); in dwc2_dump_channel_info()
420 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num)); in dwc2_dump_channel_info()
422 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); in dwc2_dump_channel_info()
423 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", in dwc2_dump_channel_info()
425 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", in dwc2_dump_channel_info()
427 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", in dwc2_dump_channel_info()
428 chan->dev_addr, chan->ep_num, chan->ep_is_in); in dwc2_dump_channel_info()
429 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); in dwc2_dump_channel_info()
430 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); in dwc2_dump_channel_info()
431 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); in dwc2_dump_channel_info()
432 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); in dwc2_dump_channel_info()
433 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); in dwc2_dump_channel_info()
434 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); in dwc2_dump_channel_info()
435 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", in dwc2_dump_channel_info()
436 (unsigned long)chan->xfer_dma); in dwc2_dump_channel_info()
437 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); in dwc2_dump_channel_info()
438 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); in dwc2_dump_channel_info()
439 dev_dbg(hsotg->dev, " NP inactive sched:\n"); in dwc2_dump_channel_info()
440 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, in dwc2_dump_channel_info()
442 dev_dbg(hsotg->dev, " %p\n", qh); in dwc2_dump_channel_info()
443 dev_dbg(hsotg->dev, " NP waiting sched:\n"); in dwc2_dump_channel_info()
444 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, in dwc2_dump_channel_info()
446 dev_dbg(hsotg->dev, " %p\n", qh); in dwc2_dump_channel_info()
447 dev_dbg(hsotg->dev, " NP active sched:\n"); in dwc2_dump_channel_info()
448 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, in dwc2_dump_channel_info()
450 dev_dbg(hsotg->dev, " %p\n", qh); in dwc2_dump_channel_info()
451 dev_dbg(hsotg->dev, " Channels:\n"); in dwc2_dump_channel_info()
453 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; in dwc2_dump_channel_info()
455 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); in dwc2_dump_channel_info()
466 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); in dwc2_host_start()
474 hcd->self.is_b_host = 0; in dwc2_host_disconnect()
482 if (urb->dev->tt) in dwc2_host_hub_info()
483 *hub_addr = urb->dev->tt->hub->devnum; in dwc2_host_hub_info()
486 *hub_port = urb->dev->ttport; in dwc2_host_hub_info()
500 switch (chan->ep_type) { in dwc2_hc_enable_slave_ints()
503 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_enable_slave_ints()
508 if (chan->ep_is_in) { in dwc2_hc_enable_slave_ints()
513 if (chan->do_ping) in dwc2_hc_enable_slave_ints()
517 if (chan->do_split) { in dwc2_hc_enable_slave_ints()
519 if (chan->complete_split) in dwc2_hc_enable_slave_ints()
525 if (chan->error_state) in dwc2_hc_enable_slave_ints()
531 dev_vdbg(hsotg->dev, "intr\n"); in dwc2_hc_enable_slave_ints()
539 if (chan->ep_is_in) in dwc2_hc_enable_slave_ints()
541 if (chan->error_state) in dwc2_hc_enable_slave_ints()
543 if (chan->do_split) { in dwc2_hc_enable_slave_ints()
544 if (chan->complete_split) in dwc2_hc_enable_slave_ints()
553 dev_vdbg(hsotg->dev, "isoc\n"); in dwc2_hc_enable_slave_ints()
558 if (chan->ep_is_in) { in dwc2_hc_enable_slave_ints()
564 dev_err(hsotg->dev, "## Unknown EP type ##\n"); in dwc2_hc_enable_slave_ints()
568 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); in dwc2_hc_enable_slave_ints()
570 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_slave_ints()
579 * For Descriptor DMA mode core halts the channel on AHB error. in dwc2_hc_enable_dma_ints()
582 if (!hsotg->params.dma_desc_enable) { in dwc2_hc_enable_dma_ints()
584 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_enable_dma_ints()
588 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_enable_dma_ints()
589 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_hc_enable_dma_ints()
593 if (chan->error_state && !chan->do_split && in dwc2_hc_enable_dma_ints()
594 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { in dwc2_hc_enable_dma_ints()
596 dev_vdbg(hsotg->dev, "setting ACK\n"); in dwc2_hc_enable_dma_ints()
598 if (chan->ep_is_in) { in dwc2_hc_enable_dma_ints()
600 if (chan->ep_type != USB_ENDPOINT_XFER_INT) in dwc2_hc_enable_dma_ints()
605 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); in dwc2_hc_enable_dma_ints()
607 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_dma_ints()
615 if (hsotg->params.host_dma) { in dwc2_hc_enable_ints()
617 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_enable_ints()
621 dev_vdbg(hsotg->dev, "DMA disabled\n"); in dwc2_hc_enable_ints()
627 intmsk |= 1 << chan->hc_num; in dwc2_hc_enable_ints()
630 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
637 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
641 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
653 u8 hc_num = chan->hc_num; in dwc2_hc_init()
659 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_init()
673 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; in dwc2_hc_init()
674 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; in dwc2_hc_init()
675 if (chan->ep_is_in) in dwc2_hc_init()
677 if (chan->speed == USB_SPEED_LOW) in dwc2_hc_init()
679 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; in dwc2_hc_init()
680 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; in dwc2_hc_init()
683 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", in dwc2_hc_init()
686 dev_vdbg(hsotg->dev, "%s: Channel %d\n", in dwc2_hc_init()
688 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", in dwc2_hc_init()
689 chan->dev_addr); in dwc2_hc_init()
690 dev_vdbg(hsotg->dev, " Ep Num: %d\n", in dwc2_hc_init()
691 chan->ep_num); in dwc2_hc_init()
692 dev_vdbg(hsotg->dev, " Is In: %d\n", in dwc2_hc_init()
693 chan->ep_is_in); in dwc2_hc_init()
694 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", in dwc2_hc_init()
695 chan->speed == USB_SPEED_LOW); in dwc2_hc_init()
696 dev_vdbg(hsotg->dev, " Ep Type: %d\n", in dwc2_hc_init()
697 chan->ep_type); in dwc2_hc_init()
698 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", in dwc2_hc_init()
699 chan->max_packet); in dwc2_hc_init()
703 if (chan->do_split) { in dwc2_hc_init()
705 dev_vdbg(hsotg->dev, in dwc2_hc_init()
706 "Programming HC %d with split --> %s\n", in dwc2_hc_init()
708 chan->complete_split ? "CSPLIT" : "SSPLIT"); in dwc2_hc_init()
709 if (chan->complete_split) in dwc2_hc_init()
711 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & in dwc2_hc_init()
713 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & in dwc2_hc_init()
715 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & in dwc2_hc_init()
718 dev_vdbg(hsotg->dev, " comp split %d\n", in dwc2_hc_init()
719 chan->complete_split); in dwc2_hc_init()
720 dev_vdbg(hsotg->dev, " xact pos %d\n", in dwc2_hc_init()
721 chan->xact_pos); in dwc2_hc_init()
722 dev_vdbg(hsotg->dev, " hub addr %d\n", in dwc2_hc_init()
723 chan->hub_addr); in dwc2_hc_init()
724 dev_vdbg(hsotg->dev, " hub port %d\n", in dwc2_hc_init()
725 chan->hub_port); in dwc2_hc_init()
726 dev_vdbg(hsotg->dev, " is_in %d\n", in dwc2_hc_init()
727 chan->ep_is_in); in dwc2_hc_init()
728 dev_vdbg(hsotg->dev, " Max Pkt %d\n", in dwc2_hc_init()
729 chan->max_packet); in dwc2_hc_init()
730 dev_vdbg(hsotg->dev, " xferlen %d\n", in dwc2_hc_init()
731 chan->xfer_len); in dwc2_hc_init()
739 * dwc2_hc_halt() - Attempts to halt a host channel
745 * This function should only be called in Slave mode or to abort a transfer in
746 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
750 * In slave mode, checks for a free request queue entry, then sets the Channel
751 * Enable and Channel Disable bits of the Host Channel Characteristics
753 * request queue entry, sets only the Channel Disable bit of the HCCHARn
758 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
772 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_halt()
775 * In buffer DMA or external DMA mode channel can't be halted in dwc2_hc_halt()
776 * for non-split periodic channels. At the end of the next in dwc2_hc_halt()
780 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || in dwc2_hc_halt()
781 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { in dwc2_hc_halt()
782 if (!chan->do_split && in dwc2_hc_halt()
783 (chan->ep_type == USB_ENDPOINT_XFER_ISOC || in dwc2_hc_halt()
784 chan->ep_type == USB_ENDPOINT_XFER_INT)) { in dwc2_hc_halt()
785 dev_err(hsotg->dev, "%s() Channel can't be halted\n", in dwc2_hc_halt()
792 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); in dwc2_hc_halt()
797 * Disable all channel interrupts except Ch Halted. The QTD in dwc2_hc_halt()
804 dev_vdbg(hsotg->dev, "dequeue/error\n"); in dwc2_hc_halt()
805 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); in dwc2_hc_halt()
812 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num)); in dwc2_hc_halt()
819 chan->halt_status = halt_status; in dwc2_hc_halt()
821 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_halt()
825 * started yet. In DMA mode, the transfer may halt if in dwc2_hc_halt()
828 * the channel again. In either Slave or DMA mode, in dwc2_hc_halt()
837 if (chan->halt_pending) { in dwc2_hc_halt()
843 dev_vdbg(hsotg->dev, in dwc2_hc_halt()
844 "*** %s: Channel %d, chan->halt_pending already set ***\n", in dwc2_hc_halt()
845 __func__, chan->hc_num); in dwc2_hc_halt()
849 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_halt()
853 if (!hsotg->params.dma_desc_enable) { in dwc2_hc_halt()
855 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_halt()
859 dev_dbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_halt()
863 if (!hsotg->params.host_dma) { in dwc2_hc_halt()
865 dev_vdbg(hsotg->dev, "DMA not enabled\n"); in dwc2_hc_halt()
869 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || in dwc2_hc_halt()
870 chan->ep_type == USB_ENDPOINT_XFER_BULK) { in dwc2_hc_halt()
871 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_halt()
874 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
879 dev_vdbg(hsotg->dev, "isoc/intr\n"); in dwc2_hc_halt()
882 hsotg->queuing_high_bandwidth) { in dwc2_hc_halt()
884 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
890 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_halt()
893 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); in dwc2_hc_halt()
894 chan->halt_status = halt_status; in dwc2_hc_halt()
898 dev_vdbg(hsotg->dev, "Channel enabled\n"); in dwc2_hc_halt()
899 chan->halt_pending = 1; in dwc2_hc_halt()
900 chan->halt_on_queue = 0; in dwc2_hc_halt()
903 dev_vdbg(hsotg->dev, "Channel disabled\n"); in dwc2_hc_halt()
904 chan->halt_on_queue = 1; in dwc2_hc_halt()
908 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_halt()
909 chan->hc_num); in dwc2_hc_halt()
910 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", in dwc2_hc_halt()
912 dev_vdbg(hsotg->dev, " halt_pending: %d\n", in dwc2_hc_halt()
913 chan->halt_pending); in dwc2_hc_halt()
914 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", in dwc2_hc_halt()
915 chan->halt_on_queue); in dwc2_hc_halt()
916 dev_vdbg(hsotg->dev, " halt_status: %d\n", in dwc2_hc_halt()
917 chan->halt_status); in dwc2_hc_halt()
922 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
934 chan->xfer_started = 0; in dwc2_hc_cleanup()
936 list_del_init(&chan->split_order_list_entry); in dwc2_hc_cleanup()
942 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num)); in dwc2_hc_cleanup()
945 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num)); in dwc2_hc_cleanup()
949 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
956 * This function has no effect on non-periodic transfers
961 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_hc_set_even_odd_frame()
962 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { in dwc2_hc_set_even_odd_frame()
995 host_speed = (chan->speed != USB_SPEED_HIGH && in dwc2_hc_set_even_odd_frame()
996 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; in dwc2_hc_set_even_odd_frame()
1002 (hsotg->params.host_perio_tx_fifo_size - in dwc2_hc_set_even_odd_frame()
1010 * transfers. This should be an over-estimate and that should in dwc2_hc_set_even_odd_frame()
1014 chan->xfer_len + bytes_in_fifo); in dwc2_hc_set_even_odd_frame()
1021 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); in dwc2_hc_set_even_odd_frame()
1033 chan->qh, wire_frame, frame_number, in dwc2_hc_set_even_odd_frame()
1046 chan->qh->next_active_frame = in dwc2_hc_set_even_odd_frame()
1060 if (chan->speed == USB_SPEED_HIGH) { in dwc2_set_pid_isoc()
1061 if (chan->ep_is_in) { in dwc2_set_pid_isoc()
1062 if (chan->multi_count == 1) in dwc2_set_pid_isoc()
1063 chan->data_pid_start = DWC2_HC_PID_DATA0; in dwc2_set_pid_isoc()
1064 else if (chan->multi_count == 2) in dwc2_set_pid_isoc()
1065 chan->data_pid_start = DWC2_HC_PID_DATA1; in dwc2_set_pid_isoc()
1067 chan->data_pid_start = DWC2_HC_PID_DATA2; in dwc2_set_pid_isoc()
1069 if (chan->multi_count == 1) in dwc2_set_pid_isoc()
1070 chan->data_pid_start = DWC2_HC_PID_DATA0; in dwc2_set_pid_isoc()
1072 chan->data_pid_start = DWC2_HC_PID_MDATA; in dwc2_set_pid_isoc()
1075 chan->data_pid_start = DWC2_HC_PID_DATA0; in dwc2_set_pid_isoc()
1080 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1086 * This function should only be called in Slave mode. For a channel associated
1087 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1100 u32 *data_buf = (u32 *)chan->xfer_buf; in dwc2_hc_write_packet()
1103 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_write_packet()
1105 remaining_count = chan->xfer_len - chan->xfer_count; in dwc2_hc_write_packet()
1106 if (remaining_count > chan->max_packet) in dwc2_hc_write_packet()
1107 byte_count = chan->max_packet; in dwc2_hc_write_packet()
1116 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num)); in dwc2_hc_write_packet()
1122 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num)); in dwc2_hc_write_packet()
1126 chan->xfer_count += byte_count; in dwc2_hc_write_packet()
1127 chan->xfer_buf += byte_count; in dwc2_hc_write_packet()
1131 * dwc2_hc_do_ping() - Starts a PING transfer
1136 * This function should only be called in Slave mode. The Do Ping bit is set in
1146 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_do_ping()
1147 chan->hc_num); in dwc2_hc_do_ping()
1151 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); in dwc2_hc_do_ping()
1153 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
1156 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
1160 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1169 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1173 * For an OUT transfer in Slave mode, it loads a data packet into the
1177 * For an IN transfer in Slave mode, a data packet is requested. The data
1181 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1186 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1195 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; in dwc2_hc_start_transfer()
1196 u16 max_hc_pkt_count = hsotg->params.max_packet_count; in dwc2_hc_start_transfer()
1203 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_start_transfer()
1205 if (chan->do_ping) { in dwc2_hc_start_transfer()
1206 if (!hsotg->params.host_dma) { in dwc2_hc_start_transfer()
1208 dev_vdbg(hsotg->dev, "ping, no DMA\n"); in dwc2_hc_start_transfer()
1210 chan->xfer_started = 1; in dwc2_hc_start_transfer()
1215 dev_vdbg(hsotg->dev, "ping, DMA\n"); in dwc2_hc_start_transfer()
1220 if (chan->do_split) { in dwc2_hc_start_transfer()
1222 dev_vdbg(hsotg->dev, "split\n"); in dwc2_hc_start_transfer()
1225 if (chan->complete_split && !chan->ep_is_in) in dwc2_hc_start_transfer()
1230 chan->xfer_len = 0; in dwc2_hc_start_transfer()
1231 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) in dwc2_hc_start_transfer()
1232 chan->xfer_len = chan->max_packet; in dwc2_hc_start_transfer()
1233 else if (!chan->ep_is_in && chan->xfer_len > 188) in dwc2_hc_start_transfer()
1234 chan->xfer_len = 188; in dwc2_hc_start_transfer()
1236 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & in dwc2_hc_start_transfer()
1240 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_hc_start_transfer()
1241 chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_hc_start_transfer()
1247 dev_vdbg(hsotg->dev, "no split\n"); in dwc2_hc_start_transfer()
1252 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_hc_start_transfer()
1253 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { in dwc2_hc_start_transfer()
1262 chan->multi_count * chan->max_packet; in dwc2_hc_start_transfer()
1264 if (chan->xfer_len > max_periodic_len) in dwc2_hc_start_transfer()
1265 chan->xfer_len = max_periodic_len; in dwc2_hc_start_transfer()
1266 } else if (chan->xfer_len > max_hc_xfer_size) { in dwc2_hc_start_transfer()
1271 chan->xfer_len = in dwc2_hc_start_transfer()
1272 max_hc_xfer_size - chan->max_packet + 1; in dwc2_hc_start_transfer()
1275 if (chan->xfer_len > 0) { in dwc2_hc_start_transfer()
1276 num_packets = (chan->xfer_len + chan->max_packet - 1) / in dwc2_hc_start_transfer()
1277 chan->max_packet; in dwc2_hc_start_transfer()
1280 chan->xfer_len = num_packets * chan->max_packet; in dwc2_hc_start_transfer()
1281 } else if (chan->ep_is_in) { in dwc2_hc_start_transfer()
1288 chan->xfer_len = num_packets * chan->max_packet; in dwc2_hc_start_transfer()
1295 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_hc_start_transfer()
1296 chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_hc_start_transfer()
1301 chan->multi_count = num_packets; in dwc2_hc_start_transfer()
1303 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_hc_start_transfer()
1306 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & in dwc2_hc_start_transfer()
1309 /* The ec_mc gets the multi_count for non-split */ in dwc2_hc_start_transfer()
1310 ec_mc = chan->multi_count; in dwc2_hc_start_transfer()
1313 chan->start_pkt_count = num_packets; in dwc2_hc_start_transfer()
1315 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & in dwc2_hc_start_transfer()
1317 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer()
1319 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", in dwc2_hc_start_transfer()
1320 hctsiz, chan->hc_num); in dwc2_hc_start_transfer()
1322 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer()
1323 chan->hc_num); in dwc2_hc_start_transfer()
1324 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", in dwc2_hc_start_transfer()
1327 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", in dwc2_hc_start_transfer()
1330 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer()
1335 if (hsotg->params.host_dma) { in dwc2_hc_start_transfer()
1338 if (chan->align_buf) { in dwc2_hc_start_transfer()
1340 dev_vdbg(hsotg->dev, "align_buf\n"); in dwc2_hc_start_transfer()
1341 dma_addr = chan->align_buf; in dwc2_hc_start_transfer()
1343 dma_addr = chan->xfer_dma; in dwc2_hc_start_transfer()
1345 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num)); in dwc2_hc_start_transfer()
1348 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", in dwc2_hc_start_transfer()
1349 (unsigned long)dma_addr, chan->hc_num); in dwc2_hc_start_transfer()
1353 if (chan->do_split) { in dwc2_hc_start_transfer()
1354 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1357 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1360 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1366 dev_warn(hsotg->dev, in dwc2_hc_start_transfer()
1368 __func__, chan->hc_num, hcchar); in dwc2_hc_start_transfer()
1375 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer()
1379 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1381 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer()
1382 chan->hc_num); in dwc2_hc_start_transfer()
1384 chan->xfer_started = 1; in dwc2_hc_start_transfer()
1385 chan->requests++; in dwc2_hc_start_transfer()
1387 if (!hsotg->params.host_dma && in dwc2_hc_start_transfer()
1388 !chan->ep_is_in && chan->xfer_len > 0) in dwc2_hc_start_transfer()
1394 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1395 * host channel and starts the transfer in Descriptor DMA mode
1402 * with micro-frame bitmap.
1413 if (chan->do_ping) in dwc2_hc_start_transfer_ddma()
1416 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_hc_start_transfer_ddma()
1419 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ in dwc2_hc_start_transfer_ddma()
1420 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & in dwc2_hc_start_transfer_ddma()
1423 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ in dwc2_hc_start_transfer_ddma()
1424 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; in dwc2_hc_start_transfer_ddma()
1426 /* Non-zero only for high-speed interrupt endpoints */ in dwc2_hc_start_transfer_ddma()
1427 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; in dwc2_hc_start_transfer_ddma()
1430 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer_ddma()
1431 chan->hc_num); in dwc2_hc_start_transfer_ddma()
1432 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer_ddma()
1433 chan->data_pid_start); in dwc2_hc_start_transfer_ddma()
1434 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); in dwc2_hc_start_transfer_ddma()
1437 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1439 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, in dwc2_hc_start_transfer_ddma()
1440 chan->desc_list_sz, DMA_TO_DEVICE); in dwc2_hc_start_transfer_ddma()
1442 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1445 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", in dwc2_hc_start_transfer_ddma()
1446 &chan->desc_list_addr, chan->hc_num); in dwc2_hc_start_transfer_ddma()
1448 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1450 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & in dwc2_hc_start_transfer_ddma()
1454 dev_warn(hsotg->dev, in dwc2_hc_start_transfer_ddma()
1456 __func__, chan->hc_num, hcchar); in dwc2_hc_start_transfer_ddma()
1463 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer_ddma()
1467 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1469 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer_ddma()
1470 chan->hc_num); in dwc2_hc_start_transfer_ddma()
1472 chan->xfer_started = 1; in dwc2_hc_start_transfer_ddma()
1473 chan->requests++; in dwc2_hc_start_transfer_ddma()
1477 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1484 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1500 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_continue_transfer()
1501 chan->hc_num); in dwc2_hc_continue_transfer()
1503 if (chan->do_split) in dwc2_hc_continue_transfer()
1507 if (chan->data_pid_start == DWC2_HC_PID_SETUP) in dwc2_hc_continue_transfer()
1511 if (chan->ep_is_in) { in dwc2_hc_continue_transfer()
1514 * back-to-back INs are issued and NAKs are received for both, in dwc2_hc_continue_transfer()
1524 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
1530 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", in dwc2_hc_continue_transfer()
1532 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
1533 chan->requests++; in dwc2_hc_continue_transfer()
1539 if (chan->xfer_count < chan->xfer_len) { in dwc2_hc_continue_transfer()
1540 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_hc_continue_transfer()
1541 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { in dwc2_hc_continue_transfer()
1543 HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
1551 chan->requests++; in dwc2_hc_continue_transfer()
1566 * -ETIMEDOUT and frees the QTD.
1577 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, in dwc2_kill_urbs_in_qh_list()
1579 dwc2_host_complete(hsotg, qtd, -ECONNRESET); in dwc2_kill_urbs_in_qh_list()
1592 if (!qh_list->next) in dwc2_qh_list_free()
1596 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_qh_list_free()
1605 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, in dwc2_qh_list_free()
1609 if (qh->channel && qh->channel->qh == qh) in dwc2_qh_list_free()
1610 qh->channel->qh = NULL; in dwc2_qh_list_free()
1612 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_qh_list_free()
1614 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_qh_list_free()
1617 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_qh_list_free()
1621 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1630 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); in dwc2_kill_all_urbs()
1631 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); in dwc2_kill_all_urbs()
1632 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); in dwc2_kill_all_urbs()
1633 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); in dwc2_kill_all_urbs()
1634 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); in dwc2_kill_all_urbs()
1635 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); in dwc2_kill_all_urbs()
1636 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); in dwc2_kill_all_urbs()
1640 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1648 if (hsotg->op_state == OTG_STATE_B_HOST) { in dwc2_hcd_start()
1650 * Reset the port. During a HNP mode switch the reset in dwc2_hcd_start()
1659 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, in dwc2_hcd_start()
1666 int num_channels = hsotg->params.host_channels; in dwc2_hcd_cleanup_channels()
1671 if (!hsotg->params.host_dma) { in dwc2_hcd_cleanup_channels()
1672 /* Flush out any channel requests in slave mode */ in dwc2_hcd_cleanup_channels()
1674 channel = hsotg->hc_ptr_array[i]; in dwc2_hcd_cleanup_channels()
1675 if (!list_empty(&channel->hc_list_entry)) in dwc2_hcd_cleanup_channels()
1687 channel = hsotg->hc_ptr_array[i]; in dwc2_hcd_cleanup_channels()
1688 if (!list_empty(&channel->hc_list_entry)) in dwc2_hcd_cleanup_channels()
1698 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); in dwc2_hcd_cleanup_channels()
1704 channel->qh = NULL; in dwc2_hcd_cleanup_channels()
1707 if (hsotg->params.uframe_sched) { in dwc2_hcd_cleanup_channels()
1708 hsotg->available_host_channels = in dwc2_hcd_cleanup_channels()
1709 hsotg->params.host_channels; in dwc2_hcd_cleanup_channels()
1711 hsotg->non_periodic_channels = 0; in dwc2_hcd_cleanup_channels()
1712 hsotg->periodic_channels = 0; in dwc2_hcd_cleanup_channels()
1717 * dwc2_hcd_connect() - Handles connect of the HCD
1725 if (hsotg->lx_state != DWC2_L0) in dwc2_hcd_connect()
1726 usb_hcd_resume_root_hub(hsotg->priv); in dwc2_hcd_connect()
1728 hsotg->flags.b.port_connect_status_change = 1; in dwc2_hcd_connect()
1729 hsotg->flags.b.port_connect_status = 1; in dwc2_hcd_connect()
1733 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1746 hsotg->flags.b.port_connect_status_change = 1; in dwc2_hcd_disconnect()
1747 hsotg->flags.b.port_connect_status = 0; in dwc2_hcd_disconnect()
1762 * mode. If still in host mode, need to keep power on to detect a in dwc2_hcd_disconnect()
1766 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { in dwc2_hcd_disconnect()
1767 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); in dwc2_hcd_disconnect()
1789 * 4. dwc2_port_intr() - clears connect interrupt in dwc2_hcd_disconnect()
1790 * 5. dwc2_handle_common_intr() - calls here in dwc2_hcd_disconnect()
1803 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1809 if (hsotg->bus_suspended) { in dwc2_hcd_rem_wakeup()
1810 hsotg->flags.b.port_suspend_change = 1; in dwc2_hcd_rem_wakeup()
1811 usb_hcd_resume_root_hub(hsotg->priv); in dwc2_hcd_rem_wakeup()
1814 if (hsotg->lx_state == DWC2_L1) in dwc2_hcd_rem_wakeup()
1815 hsotg->flags.b.port_l1_change = 1; in dwc2_hcd_rem_wakeup()
1819 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1827 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); in dwc2_hcd_stop()
1835 /* Turn off all host-specific interrupts */ in dwc2_hcd_stop()
1839 dev_dbg(hsotg->dev, "PortPower off\n"); in dwc2_hcd_stop()
1852 if (!hsotg->flags.b.port_connect_status) { in dwc2_hcd_urb_enqueue()
1854 dev_err(hsotg->dev, "Not connected\n"); in dwc2_hcd_urb_enqueue()
1855 return -ENODEV; in dwc2_hcd_urb_enqueue()
1858 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); in dwc2_hcd_urb_enqueue()
1862 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && in dwc2_hcd_urb_enqueue()
1863 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { in dwc2_hcd_urb_enqueue()
1868 return -ENODEV; in dwc2_hcd_urb_enqueue()
1872 return -EINVAL; in dwc2_hcd_urb_enqueue()
1877 dev_err(hsotg->dev, in dwc2_hcd_urb_enqueue()
1887 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && in dwc2_hcd_urb_enqueue()
1888 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) in dwc2_hcd_urb_enqueue()
1910 urb_qtd = urb->qtd; in dwc2_hcd_urb_dequeue()
1912 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); in dwc2_hcd_urb_dequeue()
1913 return -EINVAL; in dwc2_hcd_urb_dequeue()
1916 qh = urb_qtd->qh; in dwc2_hcd_urb_dequeue()
1918 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); in dwc2_hcd_urb_dequeue()
1919 return -EINVAL; in dwc2_hcd_urb_dequeue()
1922 urb->priv = NULL; in dwc2_hcd_urb_dequeue()
1924 if (urb_qtd->in_process && qh->channel) { in dwc2_hcd_urb_dequeue()
1925 dwc2_dump_channel_info(hsotg, qh->channel); in dwc2_hcd_urb_dequeue()
1928 if (hsotg->flags.b.port_connect_status) in dwc2_hcd_urb_dequeue()
1930 * If still connected (i.e. in host mode), halt the in dwc2_hcd_urb_dequeue()
1934 * device mode. in dwc2_hcd_urb_dequeue()
1936 dwc2_hc_halt(hsotg, qh->channel, in dwc2_hcd_urb_dequeue()
1944 if (!hsotg->params.dma_desc_enable) { in dwc2_hcd_urb_dequeue()
1945 u8 in_process = urb_qtd->in_process; in dwc2_hcd_urb_dequeue()
1950 qh->channel = NULL; in dwc2_hcd_urb_dequeue()
1951 } else if (list_empty(&qh->qtd_list)) { in dwc2_hcd_urb_dequeue()
1970 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_hcd_endpoint_disable()
1972 qh = ep->hcpriv; in dwc2_hcd_endpoint_disable()
1974 rc = -EINVAL; in dwc2_hcd_endpoint_disable()
1978 while (!list_empty(&qh->qtd_list) && retry--) { in dwc2_hcd_endpoint_disable()
1980 dev_err(hsotg->dev, in dwc2_hcd_endpoint_disable()
1982 rc = -EBUSY; in dwc2_hcd_endpoint_disable()
1986 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_hcd_endpoint_disable()
1988 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_hcd_endpoint_disable()
1989 qh = ep->hcpriv; in dwc2_hcd_endpoint_disable()
1991 rc = -EINVAL; in dwc2_hcd_endpoint_disable()
1999 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) in dwc2_hcd_endpoint_disable()
2002 ep->hcpriv = NULL; in dwc2_hcd_endpoint_disable()
2004 if (qh->channel && qh->channel->qh == qh) in dwc2_hcd_endpoint_disable()
2005 qh->channel->qh = NULL; in dwc2_hcd_endpoint_disable()
2007 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_hcd_endpoint_disable()
2014 ep->hcpriv = NULL; in dwc2_hcd_endpoint_disable()
2015 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_hcd_endpoint_disable()
2024 struct dwc2_qh *qh = ep->hcpriv; in dwc2_hcd_endpoint_reset()
2027 return -EINVAL; in dwc2_hcd_endpoint_reset()
2029 qh->data_toggle = DWC2_HC_PID_DATA0; in dwc2_hcd_endpoint_reset()
2035 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2036 * prepares the core for device mode or host mode operation
2046 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_init()
2052 if (hsotg->params.phy_ulpi_ext_vbus) in dwc2_core_init()
2057 if (hsotg->params.ts_dline) in dwc2_core_init()
2065 * We only need to reset the controller if this is a re-init. in dwc2_core_init()
2072 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", in dwc2_core_init()
2079 * This needs to happen in FS mode before any other programming occurs in dwc2_core_init()
2098 /* Clear the SRP success bit for FS-I2c */ in dwc2_core_init()
2099 hsotg->srp_success = 0; in dwc2_core_init()
2105 * Do device or host initialization based on mode during PCD and in dwc2_core_init()
2109 dev_dbg(hsotg->dev, "Host Mode\n"); in dwc2_core_init()
2110 hsotg->op_state = OTG_STATE_A_HOST; in dwc2_core_init()
2112 dev_dbg(hsotg->dev, "Device Mode\n"); in dwc2_core_init()
2113 hsotg->op_state = OTG_STATE_B_PERIPHERAL; in dwc2_core_init()
2120 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2121 * Host mode
2133 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_host_init()
2152 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || in dwc2_core_host_init()
2153 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { in dwc2_core_host_init()
2164 if (hsotg->params.reload_ctl) { in dwc2_core_host_init()
2170 if (hsotg->params.dma_desc_enable) { in dwc2_core_host_init()
2171 u32 op_mode = hsotg->hw_params.op_mode; in dwc2_core_host_init()
2173 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || in dwc2_core_host_init()
2174 !hsotg->hw_params.dma_desc_enable || in dwc2_core_host_init()
2178 dev_err(hsotg->dev, in dwc2_core_host_init()
2179 "Hardware does not support descriptor DMA mode -\n"); in dwc2_core_host_init()
2180 dev_err(hsotg->dev, in dwc2_core_host_init()
2181 "falling back to buffer DMA mode.\n"); in dwc2_core_host_init()
2182 hsotg->params.dma_desc_enable = false; in dwc2_core_host_init()
2193 /* TODO - check this */ in dwc2_core_host_init()
2208 if (!hsotg->params.dma_desc_enable) { in dwc2_core_host_init()
2213 num_channels = hsotg->params.host_channels; in dwc2_core_host_init()
2231 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", in dwc2_core_host_init()
2237 dev_warn(hsotg->dev, in dwc2_core_host_init()
2245 /* Enable ACG feature in host mode, if supported */ in dwc2_core_host_init()
2249 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); in dwc2_core_host_init()
2250 if (hsotg->op_state == OTG_STATE_A_HOST) { in dwc2_core_host_init()
2253 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", in dwc2_core_host_init()
2275 hsotg->flags.d32 = 0; in dwc2_hcd_reinit()
2276 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; in dwc2_hcd_reinit()
2278 if (hsotg->params.uframe_sched) { in dwc2_hcd_reinit()
2279 hsotg->available_host_channels = in dwc2_hcd_reinit()
2280 hsotg->params.host_channels; in dwc2_hcd_reinit()
2282 hsotg->non_periodic_channels = 0; in dwc2_hcd_reinit()
2283 hsotg->periodic_channels = 0; in dwc2_hcd_reinit()
2290 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, in dwc2_hcd_reinit()
2292 list_del_init(&chan->hc_list_entry); in dwc2_hcd_reinit()
2294 num_channels = hsotg->params.host_channels; in dwc2_hcd_reinit()
2296 chan = hsotg->hc_ptr_array[i]; in dwc2_hcd_reinit()
2297 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); in dwc2_hcd_reinit()
2301 /* Initialize the DWC core for host mode operation */ in dwc2_hcd_reinit()
2311 chan->do_split = 1; in dwc2_hc_init_split()
2312 chan->xact_pos = qtd->isoc_split_pos; in dwc2_hc_init_split()
2313 chan->complete_split = qtd->complete_split; in dwc2_hc_init_split()
2314 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); in dwc2_hc_init_split()
2315 chan->hub_addr = (u8)hub_addr; in dwc2_hc_init_split()
2316 chan->hub_port = (u8)hub_port; in dwc2_hc_init_split()
2323 struct dwc2_hcd_urb *urb = qtd->urb; in dwc2_hc_init_xfer()
2326 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { in dwc2_hc_init_xfer()
2328 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; in dwc2_hc_init_xfer()
2330 switch (qtd->control_phase) { in dwc2_hc_init_xfer()
2332 dev_vdbg(hsotg->dev, " Control setup transaction\n"); in dwc2_hc_init_xfer()
2333 chan->do_ping = 0; in dwc2_hc_init_xfer()
2334 chan->ep_is_in = 0; in dwc2_hc_init_xfer()
2335 chan->data_pid_start = DWC2_HC_PID_SETUP; in dwc2_hc_init_xfer()
2336 if (hsotg->params.host_dma) in dwc2_hc_init_xfer()
2337 chan->xfer_dma = urb->setup_dma; in dwc2_hc_init_xfer()
2339 chan->xfer_buf = urb->setup_packet; in dwc2_hc_init_xfer()
2340 chan->xfer_len = 8; in dwc2_hc_init_xfer()
2344 dev_vdbg(hsotg->dev, " Control data transaction\n"); in dwc2_hc_init_xfer()
2345 chan->data_pid_start = qtd->data_toggle; in dwc2_hc_init_xfer()
2353 dev_vdbg(hsotg->dev, " Control status transaction\n"); in dwc2_hc_init_xfer()
2354 if (urb->length == 0) in dwc2_hc_init_xfer()
2355 chan->ep_is_in = 1; in dwc2_hc_init_xfer()
2357 chan->ep_is_in = in dwc2_hc_init_xfer()
2358 dwc2_hcd_is_pipe_out(&urb->pipe_info); in dwc2_hc_init_xfer()
2359 if (chan->ep_is_in) in dwc2_hc_init_xfer()
2360 chan->do_ping = 0; in dwc2_hc_init_xfer()
2361 chan->data_pid_start = DWC2_HC_PID_DATA1; in dwc2_hc_init_xfer()
2362 chan->xfer_len = 0; in dwc2_hc_init_xfer()
2363 if (hsotg->params.host_dma) in dwc2_hc_init_xfer()
2364 chan->xfer_dma = hsotg->status_buf_dma; in dwc2_hc_init_xfer()
2366 chan->xfer_buf = hsotg->status_buf; in dwc2_hc_init_xfer()
2372 chan->ep_type = USB_ENDPOINT_XFER_BULK; in dwc2_hc_init_xfer()
2376 chan->ep_type = USB_ENDPOINT_XFER_INT; in dwc2_hc_init_xfer()
2380 chan->ep_type = USB_ENDPOINT_XFER_ISOC; in dwc2_hc_init_xfer()
2381 if (hsotg->params.dma_desc_enable) in dwc2_hc_init_xfer()
2384 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; in dwc2_hc_init_xfer()
2385 frame_desc->status = 0; in dwc2_hc_init_xfer()
2387 if (hsotg->params.host_dma) { in dwc2_hc_init_xfer()
2388 chan->xfer_dma = urb->dma; in dwc2_hc_init_xfer()
2389 chan->xfer_dma += frame_desc->offset + in dwc2_hc_init_xfer()
2390 qtd->isoc_split_offset; in dwc2_hc_init_xfer()
2392 chan->xfer_buf = urb->buf; in dwc2_hc_init_xfer()
2393 chan->xfer_buf += frame_desc->offset + in dwc2_hc_init_xfer()
2394 qtd->isoc_split_offset; in dwc2_hc_init_xfer()
2397 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; in dwc2_hc_init_xfer()
2399 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { in dwc2_hc_init_xfer()
2400 if (chan->xfer_len <= 188) in dwc2_hc_init_xfer()
2401 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; in dwc2_hc_init_xfer()
2403 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; in dwc2_hc_init_xfer()
2413 if (!hsotg->unaligned_cache || in dwc2_alloc_split_dma_aligned_buf()
2414 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE) in dwc2_alloc_split_dma_aligned_buf()
2415 return -ENOMEM; in dwc2_alloc_split_dma_aligned_buf()
2417 if (!qh->dw_align_buf) { in dwc2_alloc_split_dma_aligned_buf()
2418 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache, in dwc2_alloc_split_dma_aligned_buf()
2420 if (!qh->dw_align_buf) in dwc2_alloc_split_dma_aligned_buf()
2421 return -ENOMEM; in dwc2_alloc_split_dma_aligned_buf()
2424 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf, in dwc2_alloc_split_dma_aligned_buf()
2428 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { in dwc2_alloc_split_dma_aligned_buf()
2429 dev_err(hsotg->dev, "can't map align_buf\n"); in dwc2_alloc_split_dma_aligned_buf()
2430 chan->align_buf = 0; in dwc2_alloc_split_dma_aligned_buf()
2431 return -EINVAL; in dwc2_alloc_split_dma_aligned_buf()
2434 chan->align_buf = qh->dw_align_buf_dma; in dwc2_alloc_split_dma_aligned_buf()
2445 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) in dwc2_free_dma_aligned_buffer()
2448 /* Restore urb->transfer_buffer from the end of the allocated area */ in dwc2_free_dma_aligned_buffer()
2450 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length, in dwc2_free_dma_aligned_buffer()
2452 sizeof(urb->transfer_buffer)); in dwc2_free_dma_aligned_buffer()
2455 if (usb_pipeisoc(urb->pipe)) in dwc2_free_dma_aligned_buffer()
2456 length = urb->transfer_buffer_length; in dwc2_free_dma_aligned_buffer()
2458 length = urb->actual_length; in dwc2_free_dma_aligned_buffer()
2460 memcpy(stored_xfer_buffer, urb->transfer_buffer, length); in dwc2_free_dma_aligned_buffer()
2462 kfree(urb->transfer_buffer); in dwc2_free_dma_aligned_buffer()
2463 urb->transfer_buffer = stored_xfer_buffer; in dwc2_free_dma_aligned_buffer()
2465 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; in dwc2_free_dma_aligned_buffer()
2473 if (urb->num_sgs || urb->sg || in dwc2_alloc_dma_aligned_buffer()
2474 urb->transfer_buffer_length == 0 || in dwc2_alloc_dma_aligned_buffer()
2475 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) in dwc2_alloc_dma_aligned_buffer()
2483 kmalloc_size = urb->transfer_buffer_length + in dwc2_alloc_dma_aligned_buffer()
2484 (dma_get_cache_alignment() - 1) + in dwc2_alloc_dma_aligned_buffer()
2485 sizeof(urb->transfer_buffer); in dwc2_alloc_dma_aligned_buffer()
2489 return -ENOMEM; in dwc2_alloc_dma_aligned_buffer()
2492 * Position value of original urb->transfer_buffer pointer to the end in dwc2_alloc_dma_aligned_buffer()
2495 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length, in dwc2_alloc_dma_aligned_buffer()
2497 &urb->transfer_buffer, sizeof(urb->transfer_buffer)); in dwc2_alloc_dma_aligned_buffer()
2500 memcpy(kmalloc_ptr, urb->transfer_buffer, in dwc2_alloc_dma_aligned_buffer()
2501 urb->transfer_buffer_length); in dwc2_alloc_dma_aligned_buffer()
2502 urb->transfer_buffer = kmalloc_ptr; in dwc2_alloc_dma_aligned_buffer()
2504 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; in dwc2_alloc_dma_aligned_buffer()
2515 WARN_ON_ONCE(urb->setup_dma && in dwc2_map_urb_for_dma()
2516 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); in dwc2_map_urb_for_dma()
2536 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2551 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); in dwc2_assign_and_init_hc()
2553 if (list_empty(&qh->qtd_list)) { in dwc2_assign_and_init_hc()
2554 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); in dwc2_assign_and_init_hc()
2555 return -ENOMEM; in dwc2_assign_and_init_hc()
2558 if (list_empty(&hsotg->free_hc_list)) { in dwc2_assign_and_init_hc()
2559 dev_dbg(hsotg->dev, "No free channel to assign\n"); in dwc2_assign_and_init_hc()
2560 return -ENOMEM; in dwc2_assign_and_init_hc()
2563 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, in dwc2_assign_and_init_hc()
2567 list_del_init(&chan->hc_list_entry); in dwc2_assign_and_init_hc()
2569 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); in dwc2_assign_and_init_hc()
2570 urb = qtd->urb; in dwc2_assign_and_init_hc()
2571 qh->channel = chan; in dwc2_assign_and_init_hc()
2572 qtd->in_process = 1; in dwc2_assign_and_init_hc()
2578 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); in dwc2_assign_and_init_hc()
2579 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); in dwc2_assign_and_init_hc()
2580 chan->speed = qh->dev_speed; in dwc2_assign_and_init_hc()
2581 chan->max_packet = qh->maxp; in dwc2_assign_and_init_hc()
2583 chan->xfer_started = 0; in dwc2_assign_and_init_hc()
2584 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; in dwc2_assign_and_init_hc()
2585 chan->error_state = (qtd->error_count > 0); in dwc2_assign_and_init_hc()
2586 chan->halt_on_queue = 0; in dwc2_assign_and_init_hc()
2587 chan->halt_pending = 0; in dwc2_assign_and_init_hc()
2588 chan->requests = 0; in dwc2_assign_and_init_hc()
2597 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); in dwc2_assign_and_init_hc()
2598 if (chan->ep_is_in) in dwc2_assign_and_init_hc()
2599 chan->do_ping = 0; in dwc2_assign_and_init_hc()
2601 chan->do_ping = qh->ping_state; in dwc2_assign_and_init_hc()
2603 chan->data_pid_start = qh->data_toggle; in dwc2_assign_and_init_hc()
2604 chan->multi_count = 1; in dwc2_assign_and_init_hc()
2606 if (urb->actual_length > urb->length && in dwc2_assign_and_init_hc()
2607 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) in dwc2_assign_and_init_hc()
2608 urb->actual_length = urb->length; in dwc2_assign_and_init_hc()
2610 if (hsotg->params.host_dma) in dwc2_assign_and_init_hc()
2611 chan->xfer_dma = urb->dma + urb->actual_length; in dwc2_assign_and_init_hc()
2613 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; in dwc2_assign_and_init_hc()
2615 chan->xfer_len = urb->length - urb->actual_length; in dwc2_assign_and_init_hc()
2616 chan->xfer_count = 0; in dwc2_assign_and_init_hc()
2619 if (qh->do_split) in dwc2_assign_and_init_hc()
2622 chan->do_split = 0; in dwc2_assign_and_init_hc()
2627 /* For non-dword aligned buffers */ in dwc2_assign_and_init_hc()
2628 if (hsotg->params.host_dma && qh->do_split && in dwc2_assign_and_init_hc()
2629 chan->ep_is_in && (chan->xfer_dma & 0x3)) { in dwc2_assign_and_init_hc()
2630 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); in dwc2_assign_and_init_hc()
2632 dev_err(hsotg->dev, in dwc2_assign_and_init_hc()
2633 "Failed to allocate memory to handle non-aligned buffer\n"); in dwc2_assign_and_init_hc()
2635 chan->align_buf = 0; in dwc2_assign_and_init_hc()
2636 chan->multi_count = 0; in dwc2_assign_and_init_hc()
2637 list_add_tail(&chan->hc_list_entry, in dwc2_assign_and_init_hc()
2638 &hsotg->free_hc_list); in dwc2_assign_and_init_hc()
2639 qtd->in_process = 0; in dwc2_assign_and_init_hc()
2640 qh->channel = NULL; in dwc2_assign_and_init_hc()
2641 return -ENOMEM; in dwc2_assign_and_init_hc()
2645 * We assume that DMA is always aligned in non-split in dwc2_assign_and_init_hc()
2648 WARN_ON_ONCE(hsotg->params.host_dma && in dwc2_assign_and_init_hc()
2649 (chan->xfer_dma & 0x3)); in dwc2_assign_and_init_hc()
2650 chan->align_buf = 0; in dwc2_assign_and_init_hc()
2653 if (chan->ep_type == USB_ENDPOINT_XFER_INT || in dwc2_assign_and_init_hc()
2654 chan->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_assign_and_init_hc()
2659 chan->multi_count = qh->maxp_mult; in dwc2_assign_and_init_hc()
2661 if (hsotg->params.dma_desc_enable) { in dwc2_assign_and_init_hc()
2662 chan->desc_list_addr = qh->desc_list_dma; in dwc2_assign_and_init_hc()
2663 chan->desc_list_sz = qh->desc_list_sz; in dwc2_assign_and_init_hc()
2667 chan->qh = qh; in dwc2_assign_and_init_hc()
2673 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2690 dev_vdbg(hsotg->dev, " Select Transactions\n"); in dwc2_hcd_select_transactions()
2694 qh_ptr = hsotg->periodic_sched_ready.next; in dwc2_hcd_select_transactions()
2695 while (qh_ptr != &hsotg->periodic_sched_ready) { in dwc2_hcd_select_transactions()
2696 if (list_empty(&hsotg->free_hc_list)) in dwc2_hcd_select_transactions()
2698 if (hsotg->params.uframe_sched) { in dwc2_hcd_select_transactions()
2699 if (hsotg->available_host_channels <= 1) in dwc2_hcd_select_transactions()
2701 hsotg->available_host_channels--; in dwc2_hcd_select_transactions()
2711 qh_ptr = qh_ptr->next; in dwc2_hcd_select_transactions()
2712 list_move_tail(&qh->qh_list_entry, in dwc2_hcd_select_transactions()
2713 &hsotg->periodic_sched_assigned); in dwc2_hcd_select_transactions()
2718 * Process entries in the inactive portion of the non-periodic in dwc2_hcd_select_transactions()
2722 num_channels = hsotg->params.host_channels; in dwc2_hcd_select_transactions()
2723 qh_ptr = hsotg->non_periodic_sched_inactive.next; in dwc2_hcd_select_transactions()
2724 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { in dwc2_hcd_select_transactions()
2725 if (!hsotg->params.uframe_sched && in dwc2_hcd_select_transactions()
2726 hsotg->non_periodic_channels >= num_channels - in dwc2_hcd_select_transactions()
2727 hsotg->periodic_channels) in dwc2_hcd_select_transactions()
2729 if (list_empty(&hsotg->free_hc_list)) in dwc2_hcd_select_transactions()
2732 if (hsotg->params.uframe_sched) { in dwc2_hcd_select_transactions()
2733 if (hsotg->available_host_channels < 1) in dwc2_hcd_select_transactions()
2735 hsotg->available_host_channels--; in dwc2_hcd_select_transactions()
2742 * Move the QH from the non-periodic inactive schedule to the in dwc2_hcd_select_transactions()
2743 * non-periodic active schedule in dwc2_hcd_select_transactions()
2745 qh_ptr = qh_ptr->next; in dwc2_hcd_select_transactions()
2746 list_move_tail(&qh->qh_list_entry, in dwc2_hcd_select_transactions()
2747 &hsotg->non_periodic_sched_active); in dwc2_hcd_select_transactions()
2754 if (!hsotg->params.uframe_sched) in dwc2_hcd_select_transactions()
2755 hsotg->non_periodic_channels++; in dwc2_hcd_select_transactions()
2762 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2763 * a host channel associated with either a periodic or non-periodic transfer
2767 * non-periodic transfer
2769 * for periodic transfers or the non-periodic Tx FIFO
2770 * for non-periodic transfers
2774 * transfer, -1 if there is insufficient space in the Tx FIFO
2777 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2788 if (chan->do_split) in dwc2_queue_transaction()
2790 list_move_tail(&chan->split_order_list_entry, in dwc2_queue_transaction()
2791 &hsotg->split_order); in dwc2_queue_transaction()
2793 if (hsotg->params.host_dma && chan->qh) { in dwc2_queue_transaction()
2794 if (hsotg->params.dma_desc_enable) { in dwc2_queue_transaction()
2795 if (!chan->xfer_started || in dwc2_queue_transaction()
2796 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { in dwc2_queue_transaction()
2797 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); in dwc2_queue_transaction()
2798 chan->qh->ping_state = 0; in dwc2_queue_transaction()
2800 } else if (!chan->xfer_started) { in dwc2_queue_transaction()
2802 chan->qh->ping_state = 0; in dwc2_queue_transaction()
2804 } else if (chan->halt_pending) { in dwc2_queue_transaction()
2806 } else if (chan->halt_on_queue) { in dwc2_queue_transaction()
2807 dwc2_hc_halt(hsotg, chan, chan->halt_status); in dwc2_queue_transaction()
2808 } else if (chan->do_ping) { in dwc2_queue_transaction()
2809 if (!chan->xfer_started) in dwc2_queue_transaction()
2811 } else if (!chan->ep_is_in || in dwc2_queue_transaction()
2812 chan->data_pid_start == DWC2_HC_PID_SETUP) { in dwc2_queue_transaction()
2813 if ((fifo_dwords_avail * 4) >= chan->max_packet) { in dwc2_queue_transaction()
2814 if (!chan->xfer_started) { in dwc2_queue_transaction()
2821 retval = -1; in dwc2_queue_transaction()
2824 if (!chan->xfer_started) { in dwc2_queue_transaction()
2857 if (list_empty(&hsotg->periodic_sched_assigned)) in dwc2_process_periodic_channels()
2861 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); in dwc2_process_periodic_channels()
2870 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", in dwc2_process_periodic_channels()
2872 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", in dwc2_process_periodic_channels()
2876 qh_ptr = hsotg->periodic_sched_assigned.next; in dwc2_process_periodic_channels()
2877 while (qh_ptr != &hsotg->periodic_sched_assigned) { in dwc2_process_periodic_channels()
2887 if (!qh->channel) { in dwc2_process_periodic_channels()
2888 qh_ptr = qh_ptr->next; in dwc2_process_periodic_channels()
2893 if (qh->tt_buffer_dirty) { in dwc2_process_periodic_channels()
2894 qh_ptr = qh_ptr->next; in dwc2_process_periodic_channels()
2899 * Set a flag if we're queuing high-bandwidth in slave mode. in dwc2_process_periodic_channels()
2901 * the middle of multiple high-bandwidth packets getting queued. in dwc2_process_periodic_channels()
2903 if (!hsotg->params.host_dma && in dwc2_process_periodic_channels()
2904 qh->channel->multi_count > 1) in dwc2_process_periodic_channels()
2905 hsotg->queuing_high_bandwidth = 1; in dwc2_process_periodic_channels()
2909 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); in dwc2_process_periodic_channels()
2916 * In Slave mode, stay on the current transfer until there is in dwc2_process_periodic_channels()
2917 * nothing more to do or the high-bandwidth request count is in dwc2_process_periodic_channels()
2918 * reached. In DMA mode, only need to queue one request. The in dwc2_process_periodic_channels()
2920 * high-bandwidth transfers. in dwc2_process_periodic_channels()
2922 if (hsotg->params.host_dma || status == 0 || in dwc2_process_periodic_channels()
2923 qh->channel->requests == qh->channel->multi_count) { in dwc2_process_periodic_channels()
2924 qh_ptr = qh_ptr->next; in dwc2_process_periodic_channels()
2929 list_move_tail(&qh->qh_list_entry, in dwc2_process_periodic_channels()
2930 &hsotg->periodic_sched_queued); in dwc2_process_periodic_channels()
2933 hsotg->queuing_high_bandwidth = 0; in dwc2_process_periodic_channels()
2939 (!hsotg->params.host_dma && in dwc2_process_periodic_channels()
2940 !list_empty(&hsotg->periodic_sched_assigned))) { in dwc2_process_periodic_channels()
2944 * FIFO empty interrupt. (Always use the half-empty in dwc2_process_periodic_channels()
2955 * Disable the Tx FIFO empty interrupt since there are in dwc2_process_periodic_channels()
2970 * Processes active non-periodic channels and queues transactions for these
2991 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); in dwc2_process_non_periodic_channels()
2998 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", in dwc2_process_non_periodic_channels()
3000 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", in dwc2_process_non_periodic_channels()
3004 * Keep track of the starting point. Skip over the start-of-list in dwc2_process_non_periodic_channels()
3007 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) in dwc2_process_non_periodic_channels()
3008 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; in dwc2_process_non_periodic_channels()
3009 orig_qh_ptr = hsotg->non_periodic_qh_ptr; in dwc2_process_non_periodic_channels()
3019 if (!hsotg->params.host_dma && qspcavail == 0) { in dwc2_process_non_periodic_channels()
3024 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, in dwc2_process_non_periodic_channels()
3026 if (!qh->channel) in dwc2_process_non_periodic_channels()
3030 if (qh->tt_buffer_dirty) in dwc2_process_non_periodic_channels()
3035 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); in dwc2_process_non_periodic_channels()
3044 /* Advance to next QH, skipping start-of-list entry */ in dwc2_process_non_periodic_channels()
3045 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; in dwc2_process_non_periodic_channels()
3046 if (hsotg->non_periodic_qh_ptr == in dwc2_process_non_periodic_channels()
3047 &hsotg->non_periodic_sched_active) in dwc2_process_non_periodic_channels()
3048 hsotg->non_periodic_qh_ptr = in dwc2_process_non_periodic_channels()
3049 hsotg->non_periodic_qh_ptr->next; in dwc2_process_non_periodic_channels()
3050 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); in dwc2_process_non_periodic_channels()
3052 if (!hsotg->params.host_dma) { in dwc2_process_non_periodic_channels()
3058 dev_vdbg(hsotg->dev, in dwc2_process_non_periodic_channels()
3061 dev_vdbg(hsotg->dev, in dwc2_process_non_periodic_channels()
3068 * queue or Tx FIFO empties. Enable the non-periodic in dwc2_process_non_periodic_channels()
3069 * Tx FIFO empty interrupt. (Always use the half-empty in dwc2_process_non_periodic_channels()
3078 * Disable the Tx FIFO empty interrupt since there are in dwc2_process_non_periodic_channels()
3092 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3097 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3106 dev_vdbg(hsotg->dev, "Queue Transactions\n"); in dwc2_hcd_queue_transactions()
3113 /* Process host channels associated with non-periodic transfers */ in dwc2_hcd_queue_transactions()
3116 if (!list_empty(&hsotg->non_periodic_sched_active)) { in dwc2_hcd_queue_transactions()
3121 * there are no non-periodic transfers to process in dwc2_hcd_queue_transactions()
3139 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_conn_id_status_change()
3142 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); in dwc2_conn_id_status_change()
3143 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", in dwc2_conn_id_status_change()
3146 /* B-Device connector (Device Mode) */ in dwc2_conn_id_status_change()
3149 /* Wait for switch to device mode */ in dwc2_conn_id_status_change()
3150 dev_dbg(hsotg->dev, "connId B\n"); in dwc2_conn_id_status_change()
3151 if (hsotg->bus_suspended) { in dwc2_conn_id_status_change()
3152 dev_info(hsotg->dev, in dwc2_conn_id_status_change()
3153 "Do port resume before switching to device mode\n"); in dwc2_conn_id_status_change()
3157 dev_info(hsotg->dev, in dwc2_conn_id_status_change()
3158 "Waiting for Peripheral Mode, Mode=%s\n", in dwc2_conn_id_status_change()
3164 * check it again and jump to host mode if that was in dwc2_conn_id_status_change()
3174 dev_err(hsotg->dev, in dwc2_conn_id_status_change()
3182 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) in dwc2_conn_id_status_change()
3185 hsotg->op_state = OTG_STATE_B_PERIPHERAL; in dwc2_conn_id_status_change()
3188 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_conn_id_status_change()
3190 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_conn_id_status_change()
3191 /* Enable ACG feature in device mode,if supported */ in dwc2_conn_id_status_change()
3196 /* A-Device connector (Host Mode) */ in dwc2_conn_id_status_change()
3197 dev_dbg(hsotg->dev, "connId A\n"); in dwc2_conn_id_status_change()
3199 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", in dwc2_conn_id_status_change()
3207 dev_err(hsotg->dev, in dwc2_conn_id_status_change()
3210 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_conn_id_status_change()
3212 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_conn_id_status_change()
3214 hsotg->op_state = OTG_STATE_A_HOST; in dwc2_conn_id_status_change()
3215 /* Initialize the Core for Host mode */ in dwc2_conn_id_status_change()
3227 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_wakeup_detected()
3234 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); in dwc2_wakeup_detected()
3237 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", in dwc2_wakeup_detected()
3241 hsotg->bus_suspended = false; in dwc2_wakeup_detected()
3244 hsotg->lx_state = DWC2_L0; in dwc2_wakeup_detected()
3251 return hcd->self.b_hnp_enable; in dwc2_host_is_b_hnp_enabled()
3255 * dwc2_port_suspend() - Put controller in suspend mode for host.
3260 * Return: non-zero if failed to enter suspend mode for host.
3262 * This function is for entering Host mode suspend.
3272 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_port_suspend()
3274 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_port_suspend()
3276 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { in dwc2_port_suspend()
3280 hsotg->op_state = OTG_STATE_A_SUSPEND; in dwc2_port_suspend()
3283 switch (hsotg->params.power_down) { in dwc2_port_suspend()
3287 dev_err(hsotg->dev, in dwc2_port_suspend()
3295 * hibernation. in dwc2_port_suspend()
3297 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_port_suspend()
3300 dev_err(hsotg->dev, "enter hibernation failed.\n"); in dwc2_port_suspend()
3301 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_port_suspend()
3305 * If not hibernation nor partial power down are supported, in dwc2_port_suspend()
3308 if (!hsotg->params.no_clock_gating) in dwc2_port_suspend()
3319 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_port_suspend()
3323 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_port_suspend()
3330 * dwc2_port_resume() - Exit controller from suspend mode for host.
3334 * Return: non-zero if failed to exit suspend mode for host.
3336 * This function is for exiting Host mode suspend.
3344 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_port_resume()
3346 switch (hsotg->params.power_down) { in dwc2_port_resume()
3350 dev_err(hsotg->dev, in dwc2_port_resume()
3354 /* Exit host hibernation. */ in dwc2_port_resume()
3357 dev_err(hsotg->dev, "exit hibernation failed.\n"); in dwc2_port_resume()
3361 * If not hibernation nor partial power down are supported, in dwc2_port_resume()
3364 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_port_resume()
3366 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_port_resume()
3370 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_port_resume()
3375 /* Handles hub class-specific requests */
3389 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); in dwc2_hcd_hub_control()
3398 retval = -EINVAL; in dwc2_hcd_hub_control()
3399 dev_err(hsotg->dev, in dwc2_hcd_hub_control()
3411 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3419 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3422 if (hsotg->bus_suspended) in dwc2_hcd_hub_control()
3427 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3438 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3447 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3449 hsotg->flags.b.port_connect_status_change = 0; in dwc2_hcd_hub_control()
3454 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3456 hsotg->flags.b.port_reset_change = 0; in dwc2_hcd_hub_control()
3461 * Clears the driver's internal Port Enable/Disable in dwc2_hcd_hub_control()
3464 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3466 hsotg->flags.b.port_enable_change = 0; in dwc2_hcd_hub_control()
3475 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3477 hsotg->flags.b.port_suspend_change = 0; in dwc2_hcd_hub_control()
3481 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3483 hsotg->flags.b.port_l1_change = 0; in dwc2_hcd_hub_control()
3487 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3489 hsotg->flags.b.port_over_current_change = 0; in dwc2_hcd_hub_control()
3493 retval = -EINVAL; in dwc2_hcd_hub_control()
3494 dev_err(hsotg->dev, in dwc2_hcd_hub_control()
3501 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); in dwc2_hcd_hub_control()
3503 hub_desc->bDescLength = 9; in dwc2_hcd_hub_control()
3504 hub_desc->bDescriptorType = USB_DT_HUB; in dwc2_hcd_hub_control()
3505 hub_desc->bNbrPorts = 1; in dwc2_hcd_hub_control()
3506 hub_desc->wHubCharacteristics = in dwc2_hcd_hub_control()
3509 hub_desc->bPwrOn2PwrGood = 1; in dwc2_hcd_hub_control()
3510 hub_desc->bHubContrCurrent = 0; in dwc2_hcd_hub_control()
3511 hub_desc->u.hs.DeviceRemovable[0] = 0; in dwc2_hcd_hub_control()
3512 hub_desc->u.hs.DeviceRemovable[1] = 0xff; in dwc2_hcd_hub_control()
3516 dev_dbg(hsotg->dev, "GetHubStatus\n"); in dwc2_hcd_hub_control()
3521 dev_vdbg(hsotg->dev, in dwc2_hcd_hub_control()
3523 hsotg->flags.d32); in dwc2_hcd_hub_control()
3528 if (hsotg->flags.b.port_connect_status_change) in dwc2_hcd_hub_control()
3530 if (hsotg->flags.b.port_enable_change) in dwc2_hcd_hub_control()
3532 if (hsotg->flags.b.port_suspend_change) in dwc2_hcd_hub_control()
3534 if (hsotg->flags.b.port_l1_change) in dwc2_hcd_hub_control()
3536 if (hsotg->flags.b.port_reset_change) in dwc2_hcd_hub_control()
3538 if (hsotg->flags.b.port_over_current_change) { in dwc2_hcd_hub_control()
3539 dev_warn(hsotg->dev, "Overcurrent change detected\n"); in dwc2_hcd_hub_control()
3543 if (!hsotg->flags.b.port_connect_status) { in dwc2_hcd_hub_control()
3546 * either in device mode or it soon will be. Just in dwc2_hcd_hub_control()
3549 * is in device mode. in dwc2_hcd_hub_control()
3556 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); in dwc2_hcd_hub_control()
3581 if (hsotg->params.dma_desc_fs_enable) { in dwc2_hcd_hub_control()
3586 if (hsotg->new_connection && in dwc2_hcd_hub_control()
3594 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); in dwc2_hcd_hub_control()
3595 hsotg->params.dma_desc_enable = true; in dwc2_hcd_hub_control()
3599 hsotg->new_connection = false; in dwc2_hcd_hub_control()
3603 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); in dwc2_hcd_hub_control()
3608 dev_dbg(hsotg->dev, "SetHubFeature\n"); in dwc2_hcd_hub_control()
3613 dev_dbg(hsotg->dev, "SetPortFeature\n"); in dwc2_hcd_hub_control()
3617 if (!hsotg->flags.b.port_connect_status) { in dwc2_hcd_hub_control()
3620 * either in device mode or it soon will be. Just in dwc2_hcd_hub_control()
3623 * mode. in dwc2_hcd_hub_control()
3630 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3631 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); in dwc2_hcd_hub_control()
3632 if (windex != hsotg->otg_port) in dwc2_hcd_hub_control()
3634 if (!hsotg->bus_suspended) in dwc2_hcd_hub_control()
3639 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3640 "SetPortFeature - USB_PORT_FEAT_POWER\n"); in dwc2_hcd_hub_control()
3650 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3651 "SetPortFeature - USB_PORT_FEAT_RESET\n"); in dwc2_hcd_hub_control()
3655 if (hsotg->hibernated) { in dwc2_hcd_hub_control()
3658 dev_err(hsotg->dev, in dwc2_hcd_hub_control()
3659 "exit hibernation failed\n"); in dwc2_hcd_hub_control()
3662 if (hsotg->in_ppd) { in dwc2_hcd_hub_control()
3666 dev_err(hsotg->dev, in dwc2_hcd_hub_control()
3670 if (hsotg->params.power_down == in dwc2_hcd_hub_control()
3671 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) in dwc2_hcd_hub_control()
3686 * When B-Host the Port reset bit is set in the Start in dwc2_hcd_hub_control()
3692 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3693 "In host mode, hprt0=%08x\n", hprt0); in dwc2_hcd_hub_control()
3703 hsotg->lx_state = DWC2_L0; /* Now back to On state */ in dwc2_hcd_hub_control()
3707 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3708 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); in dwc2_hcd_hub_control()
3714 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3715 "SetPortFeature - USB_PORT_FEAT_TEST\n"); in dwc2_hcd_hub_control()
3722 retval = -EINVAL; in dwc2_hcd_hub_control()
3723 dev_err(hsotg->dev, in dwc2_hcd_hub_control()
3732 retval = -EINVAL; in dwc2_hcd_hub_control()
3733 dev_dbg(hsotg->dev, in dwc2_hcd_hub_control()
3747 return -EINVAL; in dwc2_hcd_is_status_changed()
3749 retval = (hsotg->flags.b.port_connect_status_change || in dwc2_hcd_is_status_changed()
3750 hsotg->flags.b.port_reset_change || in dwc2_hcd_is_status_changed()
3751 hsotg->flags.b.port_enable_change || in dwc2_hcd_is_status_changed()
3752 hsotg->flags.b.port_suspend_change || in dwc2_hcd_is_status_changed()
3753 hsotg->flags.b.port_over_current_change); in dwc2_hcd_is_status_changed()
3756 dev_dbg(hsotg->dev, in dwc2_hcd_is_status_changed()
3758 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", in dwc2_hcd_is_status_changed()
3759 hsotg->flags.b.port_connect_status_change); in dwc2_hcd_is_status_changed()
3760 dev_dbg(hsotg->dev, " port_reset_change: %d\n", in dwc2_hcd_is_status_changed()
3761 hsotg->flags.b.port_reset_change); in dwc2_hcd_is_status_changed()
3762 dev_dbg(hsotg->dev, " port_enable_change: %d\n", in dwc2_hcd_is_status_changed()
3763 hsotg->flags.b.port_enable_change); in dwc2_hcd_is_status_changed()
3764 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", in dwc2_hcd_is_status_changed()
3765 hsotg->flags.b.port_suspend_change); in dwc2_hcd_is_status_changed()
3766 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", in dwc2_hcd_is_status_changed()
3767 hsotg->flags.b.port_over_current_change); in dwc2_hcd_is_status_changed()
3778 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", in dwc2_hcd_get_frame_number()
3807 phy_clks = (interval - remaining) + in dwc2_hcd_get_future_frame_number()
3815 return hsotg->op_state == OTG_STATE_B_HOST; in dwc2_hcd_is_b_host()
3826 urb->packet_count = iso_desc_count; in dwc2_hcd_urb_alloc()
3838 dev_vdbg(hsotg->dev, in dwc2_hcd_urb_set_pipeinfo()
3841 urb->pipe_info.dev_addr = dev_addr; in dwc2_hcd_urb_set_pipeinfo()
3842 urb->pipe_info.ep_num = ep_num; in dwc2_hcd_urb_set_pipeinfo()
3843 urb->pipe_info.pipe_type = ep_type; in dwc2_hcd_urb_set_pipeinfo()
3844 urb->pipe_info.pipe_dir = ep_dir; in dwc2_hcd_urb_set_pipeinfo()
3845 urb->pipe_info.maxp = maxp; in dwc2_hcd_urb_set_pipeinfo()
3846 urb->pipe_info.maxp_mult = maxp_mult; in dwc2_hcd_urb_set_pipeinfo()
3864 num_channels = hsotg->params.host_channels; in dwc2_hcd_dump_state()
3865 dev_dbg(hsotg->dev, "\n"); in dwc2_hcd_dump_state()
3866 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3868 dev_dbg(hsotg->dev, "HCD State:\n"); in dwc2_hcd_dump_state()
3869 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); in dwc2_hcd_dump_state()
3872 chan = hsotg->hc_ptr_array[i]; in dwc2_hcd_dump_state()
3873 dev_dbg(hsotg->dev, " Channel %d:\n", i); in dwc2_hcd_dump_state()
3874 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3876 chan->dev_addr, chan->ep_num, chan->ep_is_in); in dwc2_hcd_dump_state()
3877 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); in dwc2_hcd_dump_state()
3878 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); in dwc2_hcd_dump_state()
3879 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); in dwc2_hcd_dump_state()
3880 dev_dbg(hsotg->dev, " data_pid_start: %d\n", in dwc2_hcd_dump_state()
3881 chan->data_pid_start); in dwc2_hcd_dump_state()
3882 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); in dwc2_hcd_dump_state()
3883 dev_dbg(hsotg->dev, " xfer_started: %d\n", in dwc2_hcd_dump_state()
3884 chan->xfer_started); in dwc2_hcd_dump_state()
3885 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); in dwc2_hcd_dump_state()
3886 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", in dwc2_hcd_dump_state()
3887 (unsigned long)chan->xfer_dma); in dwc2_hcd_dump_state()
3888 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); in dwc2_hcd_dump_state()
3889 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); in dwc2_hcd_dump_state()
3890 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", in dwc2_hcd_dump_state()
3891 chan->halt_on_queue); in dwc2_hcd_dump_state()
3892 dev_dbg(hsotg->dev, " halt_pending: %d\n", in dwc2_hcd_dump_state()
3893 chan->halt_pending); in dwc2_hcd_dump_state()
3894 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); in dwc2_hcd_dump_state()
3895 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); in dwc2_hcd_dump_state()
3896 dev_dbg(hsotg->dev, " complete_split: %d\n", in dwc2_hcd_dump_state()
3897 chan->complete_split); in dwc2_hcd_dump_state()
3898 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); in dwc2_hcd_dump_state()
3899 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); in dwc2_hcd_dump_state()
3900 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); in dwc2_hcd_dump_state()
3901 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); in dwc2_hcd_dump_state()
3902 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); in dwc2_hcd_dump_state()
3904 if (chan->xfer_started) { in dwc2_hcd_dump_state()
3912 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); in dwc2_hcd_dump_state()
3913 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); in dwc2_hcd_dump_state()
3914 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); in dwc2_hcd_dump_state()
3915 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); in dwc2_hcd_dump_state()
3916 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); in dwc2_hcd_dump_state()
3919 if (!(chan->xfer_started && chan->qh)) in dwc2_hcd_dump_state()
3922 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { in dwc2_hcd_dump_state()
3923 if (!qtd->in_process) in dwc2_hcd_dump_state()
3925 urb = qtd->urb; in dwc2_hcd_dump_state()
3926 dev_dbg(hsotg->dev, " URB Info:\n"); in dwc2_hcd_dump_state()
3927 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", in dwc2_hcd_dump_state()
3930 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3932 dwc2_hcd_get_dev_addr(&urb->pipe_info), in dwc2_hcd_dump_state()
3933 dwc2_hcd_get_ep_num(&urb->pipe_info), in dwc2_hcd_dump_state()
3934 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? in dwc2_hcd_dump_state()
3936 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3938 dwc2_hcd_get_maxp(&urb->pipe_info), in dwc2_hcd_dump_state()
3939 dwc2_hcd_get_maxp_mult(&urb->pipe_info)); in dwc2_hcd_dump_state()
3940 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3942 urb->buf); in dwc2_hcd_dump_state()
3943 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3945 (unsigned long)urb->dma); in dwc2_hcd_dump_state()
3946 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3948 urb->length); in dwc2_hcd_dump_state()
3949 dev_dbg(hsotg->dev, " actual_length: %d\n", in dwc2_hcd_dump_state()
3950 urb->actual_length); in dwc2_hcd_dump_state()
3955 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", in dwc2_hcd_dump_state()
3956 hsotg->non_periodic_channels); in dwc2_hcd_dump_state()
3957 dev_dbg(hsotg->dev, " periodic_channels: %d\n", in dwc2_hcd_dump_state()
3958 hsotg->periodic_channels); in dwc2_hcd_dump_state()
3959 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); in dwc2_hcd_dump_state()
3961 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", in dwc2_hcd_dump_state()
3963 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", in dwc2_hcd_dump_state()
3966 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", in dwc2_hcd_dump_state()
3968 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", in dwc2_hcd_dump_state()
3972 dev_dbg(hsotg->dev, in dwc2_hcd_dump_state()
3974 dev_dbg(hsotg->dev, "\n"); in dwc2_hcd_dump_state()
3987 p = (struct wrapper_priv_data *)&hcd->hcd_priv; in dwc2_hcd_to_hsotg()
3988 return p->hsotg; in dwc2_hcd_to_hsotg()
3992 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4017 if (urb->dev->tt) { in dwc2_host_get_tt_info()
4018 *ttport = urb->dev->ttport; in dwc2_host_get_tt_info()
4020 dwc_tt = urb->dev->tt->hcpriv; in dwc2_host_get_tt_info()
4029 sizeof(dwc_tt->periodic_bitmaps[0]); in dwc2_host_get_tt_info()
4030 if (urb->dev->tt->multi) in dwc2_host_get_tt_info()
4031 bitmap_size *= urb->dev->tt->hub->maxchild; in dwc2_host_get_tt_info()
4038 dwc_tt->usb_tt = urb->dev->tt; in dwc2_host_get_tt_info()
4039 dwc_tt->usb_tt->hcpriv = dwc_tt; in dwc2_host_get_tt_info()
4042 dwc_tt->refcount++; in dwc2_host_get_tt_info()
4049 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4061 /* Model kfree and make put of NULL a no-op */ in dwc2_host_put_tt_info()
4065 WARN_ON(dwc_tt->refcount < 1); in dwc2_host_put_tt_info()
4067 dwc_tt->refcount--; in dwc2_host_put_tt_info()
4068 if (!dwc_tt->refcount) { in dwc2_host_put_tt_info()
4069 dwc_tt->usb_tt->hcpriv = NULL; in dwc2_host_put_tt_info()
4078 return urb->dev->speed; in dwc2_host_get_speed()
4086 if (urb->interval) in dwc2_allocate_bus_bandwidth()
4087 bus->bandwidth_allocated += bw / urb->interval; in dwc2_allocate_bus_bandwidth()
4088 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) in dwc2_allocate_bus_bandwidth()
4089 bus->bandwidth_isoc_reqs++; in dwc2_allocate_bus_bandwidth()
4091 bus->bandwidth_int_reqs++; in dwc2_allocate_bus_bandwidth()
4099 if (urb->interval) in dwc2_free_bus_bandwidth()
4100 bus->bandwidth_allocated -= bw / urb->interval; in dwc2_free_bus_bandwidth()
4101 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) in dwc2_free_bus_bandwidth()
4102 bus->bandwidth_isoc_reqs--; in dwc2_free_bus_bandwidth()
4104 bus->bandwidth_int_reqs--; in dwc2_free_bus_bandwidth()
4120 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); in dwc2_host_complete()
4124 if (!qtd->urb) { in dwc2_host_complete()
4125 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); in dwc2_host_complete()
4129 urb = qtd->urb->priv; in dwc2_host_complete()
4131 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); in dwc2_host_complete()
4135 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); in dwc2_host_complete()
4138 dev_vdbg(hsotg->dev, in dwc2_host_complete()
4139 "%s: urb %p device %d ep %d-%s status %d actual %d\n", in dwc2_host_complete()
4140 __func__, urb, usb_pipedevice(urb->pipe), in dwc2_host_complete()
4141 usb_pipeendpoint(urb->pipe), in dwc2_host_complete()
4142 usb_pipein(urb->pipe) ? "IN" : "OUT", status, in dwc2_host_complete()
4143 urb->actual_length); in dwc2_host_complete()
4145 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { in dwc2_host_complete()
4146 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); in dwc2_host_complete()
4147 for (i = 0; i < urb->number_of_packets; ++i) { in dwc2_host_complete()
4148 urb->iso_frame_desc[i].actual_length = in dwc2_host_complete()
4150 qtd->urb, i); in dwc2_host_complete()
4151 urb->iso_frame_desc[i].status = in dwc2_host_complete()
4152 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); in dwc2_host_complete()
4156 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { in dwc2_host_complete()
4157 for (i = 0; i < urb->number_of_packets; i++) in dwc2_host_complete()
4158 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", in dwc2_host_complete()
4159 i, urb->iso_frame_desc[i].status); in dwc2_host_complete()
4162 urb->status = status; in dwc2_host_complete()
4164 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && in dwc2_host_complete()
4165 urb->actual_length < urb->transfer_buffer_length) in dwc2_host_complete()
4166 urb->status = -EREMOTEIO; in dwc2_host_complete()
4169 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || in dwc2_host_complete()
4170 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { in dwc2_host_complete()
4171 struct usb_host_endpoint *ep = urb->ep; in dwc2_host_complete()
4180 urb->hcpriv = NULL; in dwc2_host_complete()
4181 kfree(qtd->urb); in dwc2_host_complete()
4182 qtd->urb = NULL; in dwc2_host_complete()
4188 * Work queue function for starting the HCD when A-Cable is connected
4195 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); in dwc2_hcd_start_func()
4209 dev_dbg(hsotg->dev, "USB RESET function called\n"); in dwc2_hcd_reset_func()
4211 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_hcd_reset_func()
4216 hsotg->flags.b.port_reset_change = 1; in dwc2_hcd_reset_func()
4218 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_hcd_reset_func()
4227 ret = phy_reset(hsotg->phy); in dwc2_hcd_phy_reset_func()
4229 dev_warn(hsotg->dev, "PHY reset failed\n"); in dwc2_hcd_phy_reset_func()
4240 * mode operation. Activates the root port. Returns 0 on success and a negative
4251 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); in _dwc2_hcd_start()
4253 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_start()
4254 hsotg->lx_state = DWC2_L0; in _dwc2_hcd_start()
4255 hcd->state = HC_STATE_RUNNING; in _dwc2_hcd_start()
4256 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_start()
4259 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_start()
4269 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_start()
4273 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_start()
4277 if (bus->root_hub) { in _dwc2_hcd_start()
4278 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); in _dwc2_hcd_start()
4283 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_start()
4289 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4298 /* Turn off all host-specific interrupts */ in _dwc2_hcd_stop()
4302 synchronize_irq(hcd->irq); in _dwc2_hcd_stop()
4304 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_stop()
4309 hsotg->lx_state = DWC2_L3; in _dwc2_hcd_stop()
4310 hcd->state = HC_STATE_HALT; in _dwc2_hcd_stop()
4311 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_stop()
4312 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_stop()
4327 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4332 if (hsotg->lx_state != DWC2_L0) in _dwc2_hcd_suspend()
4338 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) in _dwc2_hcd_suspend()
4341 if (hsotg->bus_suspended) in _dwc2_hcd_suspend()
4344 if (hsotg->flags.b.port_connect_status == 0) in _dwc2_hcd_suspend()
4347 switch (hsotg->params.power_down) { in _dwc2_hcd_suspend()
4352 dev_err(hsotg->dev, in _dwc2_hcd_suspend()
4355 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_suspend()
4358 /* Enter hibernation */ in _dwc2_hcd_suspend()
4359 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4362 dev_err(hsotg->dev, "enter hibernation failed\n"); in _dwc2_hcd_suspend()
4363 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4366 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_suspend()
4370 * If not hibernation nor partial power down are supported, in _dwc2_hcd_suspend()
4373 if (!hsotg->params.no_clock_gating) { in _dwc2_hcd_suspend()
4377 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_suspend()
4384 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4386 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4389 if (!IS_ERR_OR_NULL(hsotg->uphy)) { in _dwc2_hcd_suspend()
4390 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4391 usb_phy_set_suspend(hsotg->uphy, true); in _dwc2_hcd_suspend()
4392 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4396 hsotg->lx_state = DWC2_L2; in _dwc2_hcd_suspend()
4398 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_suspend()
4410 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_resume()
4415 if (hsotg->lx_state != DWC2_L2) in _dwc2_hcd_resume()
4422 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial in _dwc2_hcd_resume()
4423 * Power Down mode. in _dwc2_hcd_resume()
4426 hsotg->lx_state = DWC2_L0; in _dwc2_hcd_resume()
4430 switch (hsotg->params.power_down) { in _dwc2_hcd_resume()
4434 dev_err(hsotg->dev, in _dwc2_hcd_resume()
4440 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_resume()
4445 dev_err(hsotg->dev, "exit hibernation failed.\n"); in _dwc2_hcd_resume()
4451 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_resume()
4455 * If not hibernation nor partial power down are supported, in _dwc2_hcd_resume()
4458 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_resume()
4462 * Initialize the Core for Host mode, as after system resume in _dwc2_hcd_resume()
4468 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_resume()
4474 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); in _dwc2_hcd_resume()
4477 hsotg->lx_state = DWC2_L0; in _dwc2_hcd_resume()
4482 hsotg->flags.b.port_suspend_change = 1; in _dwc2_hcd_resume()
4489 if (!IS_ERR_OR_NULL(hsotg->uphy)) { in _dwc2_hcd_resume()
4490 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_resume()
4491 usb_phy_set_suspend(hsotg->uphy, false); in _dwc2_hcd_resume()
4492 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_resume()
4496 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_resume()
4499 /* Wait for controller to correctly update D+/D- level */ in _dwc2_hcd_resume()
4501 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_resume()
4511 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_resume()
4513 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_resume()
4515 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_resume()
4536 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); in dwc2_dump_urb_info()
4537 dev_vdbg(hsotg->dev, " Device address: %d\n", in dwc2_dump_urb_info()
4538 usb_pipedevice(urb->pipe)); in dwc2_dump_urb_info()
4539 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", in dwc2_dump_urb_info()
4540 usb_pipeendpoint(urb->pipe), in dwc2_dump_urb_info()
4541 usb_pipein(urb->pipe) ? "IN" : "OUT"); in dwc2_dump_urb_info()
4543 switch (usb_pipetype(urb->pipe)) { in dwc2_dump_urb_info()
4558 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, in dwc2_dump_urb_info()
4559 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? in dwc2_dump_urb_info()
4562 switch (urb->dev->speed) { in dwc2_dump_urb_info()
4577 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); in dwc2_dump_urb_info()
4578 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n", in dwc2_dump_urb_info()
4579 usb_endpoint_maxp(&urb->ep->desc), in dwc2_dump_urb_info()
4580 usb_endpoint_maxp_mult(&urb->ep->desc)); in dwc2_dump_urb_info()
4582 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", in dwc2_dump_urb_info()
4583 urb->transfer_buffer_length); in dwc2_dump_urb_info()
4584 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", in dwc2_dump_urb_info()
4585 urb->transfer_buffer, (unsigned long)urb->transfer_dma); in dwc2_dump_urb_info()
4586 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", in dwc2_dump_urb_info()
4587 urb->setup_packet, (unsigned long)urb->setup_dma); in dwc2_dump_urb_info()
4588 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); in dwc2_dump_urb_info()
4590 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { in dwc2_dump_urb_info()
4593 for (i = 0; i < urb->number_of_packets; i++) { in dwc2_dump_urb_info()
4594 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); in dwc2_dump_urb_info()
4595 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", in dwc2_dump_urb_info()
4596 urb->iso_frame_desc[i].offset, in dwc2_dump_urb_info()
4597 urb->iso_frame_desc[i].length); in dwc2_dump_urb_info()
4612 struct usb_host_endpoint *ep = urb->ep; in _dwc2_hcd_urb_enqueue()
4626 gr = &hsotg->gr_backup; in _dwc2_hcd_urb_enqueue()
4629 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); in _dwc2_hcd_urb_enqueue()
4633 if (hsotg->hibernated) { in _dwc2_hcd_urb_enqueue()
4634 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) in _dwc2_hcd_urb_enqueue()
4640 dev_err(hsotg->dev, in _dwc2_hcd_urb_enqueue()
4641 "exit hibernation failed.\n"); in _dwc2_hcd_urb_enqueue()
4644 if (hsotg->in_ppd) { in _dwc2_hcd_urb_enqueue()
4647 dev_err(hsotg->dev, in _dwc2_hcd_urb_enqueue()
4651 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && in _dwc2_hcd_urb_enqueue()
4652 hsotg->bus_suspended) { in _dwc2_hcd_urb_enqueue()
4660 return -EINVAL; in _dwc2_hcd_urb_enqueue()
4662 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || in _dwc2_hcd_urb_enqueue()
4663 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { in _dwc2_hcd_urb_enqueue()
4664 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_urb_enqueue()
4667 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_urb_enqueue()
4670 switch (usb_pipetype(urb->pipe)) { in _dwc2_hcd_urb_enqueue()
4685 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, in _dwc2_hcd_urb_enqueue()
4688 return -ENOMEM; in _dwc2_hcd_urb_enqueue()
4690 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), in _dwc2_hcd_urb_enqueue()
4691 usb_pipeendpoint(urb->pipe), ep_type, in _dwc2_hcd_urb_enqueue()
4692 usb_pipein(urb->pipe), in _dwc2_hcd_urb_enqueue()
4693 usb_endpoint_maxp(&ep->desc), in _dwc2_hcd_urb_enqueue()
4694 usb_endpoint_maxp_mult(&ep->desc)); in _dwc2_hcd_urb_enqueue()
4696 buf = urb->transfer_buffer; in _dwc2_hcd_urb_enqueue()
4699 if (!buf && (urb->transfer_dma & 3)) { in _dwc2_hcd_urb_enqueue()
4700 dev_err(hsotg->dev, in _dwc2_hcd_urb_enqueue()
4703 retval = -EINVAL; in _dwc2_hcd_urb_enqueue()
4708 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) in _dwc2_hcd_urb_enqueue()
4710 if (urb->transfer_flags & URB_ZERO_PACKET) in _dwc2_hcd_urb_enqueue()
4713 dwc2_urb->priv = urb; in _dwc2_hcd_urb_enqueue()
4714 dwc2_urb->buf = buf; in _dwc2_hcd_urb_enqueue()
4715 dwc2_urb->dma = urb->transfer_dma; in _dwc2_hcd_urb_enqueue()
4716 dwc2_urb->length = urb->transfer_buffer_length; in _dwc2_hcd_urb_enqueue()
4717 dwc2_urb->setup_packet = urb->setup_packet; in _dwc2_hcd_urb_enqueue()
4718 dwc2_urb->setup_dma = urb->setup_dma; in _dwc2_hcd_urb_enqueue()
4719 dwc2_urb->flags = tflags; in _dwc2_hcd_urb_enqueue()
4720 dwc2_urb->interval = urb->interval; in _dwc2_hcd_urb_enqueue()
4721 dwc2_urb->status = -EINPROGRESS; in _dwc2_hcd_urb_enqueue()
4723 for (i = 0; i < urb->number_of_packets; ++i) in _dwc2_hcd_urb_enqueue()
4725 urb->iso_frame_desc[i].offset, in _dwc2_hcd_urb_enqueue()
4726 urb->iso_frame_desc[i].length); in _dwc2_hcd_urb_enqueue()
4728 urb->hcpriv = dwc2_urb; in _dwc2_hcd_urb_enqueue()
4729 qh = (struct dwc2_qh *)ep->hcpriv; in _dwc2_hcd_urb_enqueue()
4734 retval = -ENOMEM; in _dwc2_hcd_urb_enqueue()
4737 ep->hcpriv = qh; in _dwc2_hcd_urb_enqueue()
4743 retval = -ENOMEM; in _dwc2_hcd_urb_enqueue()
4747 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_urb_enqueue()
4762 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_urb_enqueue()
4767 dwc2_urb->priv = NULL; in _dwc2_hcd_urb_enqueue()
4769 if (qh_allocated && qh->channel && qh->channel->qh == qh) in _dwc2_hcd_urb_enqueue()
4770 qh->channel->qh = NULL; in _dwc2_hcd_urb_enqueue()
4772 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_urb_enqueue()
4773 urb->hcpriv = NULL; in _dwc2_hcd_urb_enqueue()
4779 ep->hcpriv = NULL; in _dwc2_hcd_urb_enqueue()
4782 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, in _dwc2_hcd_urb_enqueue()
4803 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); in _dwc2_hcd_urb_dequeue()
4806 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_urb_dequeue()
4812 if (!urb->hcpriv) { in _dwc2_hcd_urb_dequeue()
4813 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); in _dwc2_hcd_urb_dequeue()
4817 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); in _dwc2_hcd_urb_dequeue()
4821 kfree(urb->hcpriv); in _dwc2_hcd_urb_dequeue()
4822 urb->hcpriv = NULL; in _dwc2_hcd_urb_dequeue()
4825 spin_unlock(&hsotg->lock); in _dwc2_hcd_urb_dequeue()
4827 spin_lock(&hsotg->lock); in _dwc2_hcd_urb_dequeue()
4829 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); in _dwc2_hcd_urb_dequeue()
4830 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); in _dwc2_hcd_urb_dequeue()
4832 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_urb_dequeue()
4847 dev_dbg(hsotg->dev, in _dwc2_hcd_endpoint_disable()
4848 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", in _dwc2_hcd_endpoint_disable()
4849 ep->desc.bEndpointAddress, ep->hcpriv); in _dwc2_hcd_endpoint_disable()
4864 dev_dbg(hsotg->dev, in _dwc2_hcd_endpoint_reset()
4866 ep->desc.bEndpointAddress); in _dwc2_hcd_endpoint_reset()
4868 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_endpoint_reset()
4870 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_endpoint_reset()
4874 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4901 /* Handles hub class-specific requests */
4918 qh = ep->hcpriv; in _dwc2_hcd_clear_tt_buffer_complete()
4922 spin_lock_irqsave(&hsotg->lock, flags); in _dwc2_hcd_clear_tt_buffer_complete()
4923 qh->tt_buffer_dirty = 0; in _dwc2_hcd_clear_tt_buffer_complete()
4925 if (hsotg->flags.b.port_connect_status) in _dwc2_hcd_clear_tt_buffer_complete()
4928 spin_unlock_irqrestore(&hsotg->lock, flags); in _dwc2_hcd_clear_tt_buffer_complete()
4939 if (hsotg->params.speed == speed) in dwc2_change_bus_speed()
4942 hsotg->params.speed = speed; in dwc2_change_bus_speed()
4943 queue_work(hsotg->wq_otg, &hsotg->wf_otg); in dwc2_change_bus_speed()
4950 if (!hsotg->params.change_speed_quirk) in dwc2_free_dev()
4954 * On removal, set speed to default high-speed. in dwc2_free_dev()
4956 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && in dwc2_free_dev()
4957 udev->parent->speed < USB_SPEED_HIGH) { in dwc2_free_dev()
4958 dev_info(hsotg->dev, "Set speed to default high-speed\n"); in dwc2_free_dev()
4967 if (!hsotg->params.change_speed_quirk) in dwc2_reset_device()
4970 if (udev->speed == USB_SPEED_HIGH) { in dwc2_reset_device()
4971 dev_info(hsotg->dev, "Set speed to high-speed\n"); in dwc2_reset_device()
4973 } else if ((udev->speed == USB_SPEED_FULL || in dwc2_reset_device()
4974 udev->speed == USB_SPEED_LOW)) { in dwc2_reset_device()
4976 * Change speed setting to full-speed if there's in dwc2_reset_device()
4977 * a full-speed or low-speed device plugged in. in dwc2_reset_device()
4979 dev_info(hsotg->dev, "Set speed to full-speed\n"); in dwc2_reset_device()
5023 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); in dwc2_hcd_free()
5026 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); in dwc2_hcd_free()
5027 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); in dwc2_hcd_free()
5028 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); in dwc2_hcd_free()
5029 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); in dwc2_hcd_free()
5030 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); in dwc2_hcd_free()
5031 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); in dwc2_hcd_free()
5032 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); in dwc2_hcd_free()
5036 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; in dwc2_hcd_free()
5039 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", in dwc2_hcd_free()
5041 hsotg->hc_ptr_array[i] = NULL; in dwc2_hcd_free()
5046 if (hsotg->params.host_dma) { in dwc2_hcd_free()
5047 if (hsotg->status_buf) { in dwc2_hcd_free()
5048 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, in dwc2_hcd_free()
5049 hsotg->status_buf, in dwc2_hcd_free()
5050 hsotg->status_buf_dma); in dwc2_hcd_free()
5051 hsotg->status_buf = NULL; in dwc2_hcd_free()
5054 kfree(hsotg->status_buf); in dwc2_hcd_free()
5055 hsotg->status_buf = NULL; in dwc2_hcd_free()
5060 /* Disable all interrupts */ in dwc2_hcd_free()
5065 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { in dwc2_hcd_free()
5071 if (hsotg->wq_otg) { in dwc2_hcd_free()
5072 if (!cancel_work_sync(&hsotg->wf_otg)) in dwc2_hcd_free()
5073 flush_workqueue(hsotg->wq_otg); in dwc2_hcd_free()
5074 destroy_workqueue(hsotg->wq_otg); in dwc2_hcd_free()
5077 cancel_work_sync(&hsotg->phy_reset_work); in dwc2_hcd_free()
5079 del_timer(&hsotg->wkp_timer); in dwc2_hcd_free()
5084 /* Turn off all host-specific interrupts */ in dwc2_hcd_release()
5093 * USB bus with the core and calls the hc_driver->start() function. It returns
5098 struct platform_device *pdev = to_platform_device(hsotg->dev); in dwc2_hcd_init()
5107 return -ENODEV; in dwc2_hcd_init()
5109 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); in dwc2_hcd_init()
5111 retval = -ENOMEM; in dwc2_hcd_init()
5114 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); in dwc2_hcd_init()
5117 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE, in dwc2_hcd_init()
5118 sizeof(*hsotg->frame_num_array), in dwc2_hcd_init()
5120 if (!hsotg->frame_num_array) in dwc2_hcd_init()
5122 hsotg->last_frame_num_array = in dwc2_hcd_init()
5124 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL); in dwc2_hcd_init()
5125 if (!hsotg->last_frame_num_array) in dwc2_hcd_init()
5128 hsotg->last_frame_num = HFNUM_MAX_FRNUM; in dwc2_hcd_init()
5131 if (hsotg->params.host_dma && in dwc2_hcd_init()
5132 !hsotg->dev->dma_mask) { in dwc2_hcd_init()
5133 dev_warn(hsotg->dev, in dwc2_hcd_init()
5135 hsotg->params.host_dma = false; in dwc2_hcd_init()
5136 hsotg->params.dma_desc_enable = false; in dwc2_hcd_init()
5140 if (hsotg->params.host_dma) { in dwc2_hcd_init()
5141 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) in dwc2_hcd_init()
5142 dev_warn(hsotg->dev, "can't set DMA mask\n"); in dwc2_hcd_init()
5143 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) in dwc2_hcd_init()
5144 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); in dwc2_hcd_init()
5147 if (hsotg->params.change_speed_quirk) { in dwc2_hcd_init()
5152 if (hsotg->params.host_dma) in dwc2_hcd_init()
5155 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); in dwc2_hcd_init()
5159 hcd->has_tt = 1; in dwc2_hcd_init()
5163 retval = -EINVAL; in dwc2_hcd_init()
5166 hcd->rsrc_start = res->start; in dwc2_hcd_init()
5167 hcd->rsrc_len = resource_size(res); in dwc2_hcd_init()
5169 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; in dwc2_hcd_init()
5170 hsotg->priv = hcd; in dwc2_hcd_init()
5173 * Disable the global interrupt until all the interrupt handlers are in dwc2_hcd_init()
5184 retval = -ENOMEM; in dwc2_hcd_init()
5185 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); in dwc2_hcd_init()
5186 if (!hsotg->wq_otg) { in dwc2_hcd_init()
5187 dev_err(hsotg->dev, "Failed to create workqueue\n"); in dwc2_hcd_init()
5190 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); in dwc2_hcd_init()
5192 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); in dwc2_hcd_init()
5194 /* Initialize the non-periodic schedule */ in dwc2_hcd_init()
5195 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); in dwc2_hcd_init()
5196 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); in dwc2_hcd_init()
5197 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); in dwc2_hcd_init()
5200 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); in dwc2_hcd_init()
5201 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); in dwc2_hcd_init()
5202 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); in dwc2_hcd_init()
5203 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); in dwc2_hcd_init()
5205 INIT_LIST_HEAD(&hsotg->split_order); in dwc2_hcd_init()
5211 INIT_LIST_HEAD(&hsotg->free_hc_list); in dwc2_hcd_init()
5212 num_channels = hsotg->params.host_channels; in dwc2_hcd_init()
5213 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); in dwc2_hcd_init()
5219 channel->hc_num = i; in dwc2_hcd_init()
5220 INIT_LIST_HEAD(&channel->split_order_list_entry); in dwc2_hcd_init()
5221 hsotg->hc_ptr_array[i] = channel; in dwc2_hcd_init()
5225 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); in dwc2_hcd_init()
5226 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); in dwc2_hcd_init()
5227 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func); in dwc2_hcd_init()
5235 if (hsotg->params.host_dma) in dwc2_hcd_init()
5236 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, in dwc2_hcd_init()
5238 &hsotg->status_buf_dma, GFP_KERNEL); in dwc2_hcd_init()
5240 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, in dwc2_hcd_init()
5243 if (!hsotg->status_buf) in dwc2_hcd_init()
5248 * DMA mode. in dwc2_hcd_init()
5251 if (hsotg->params.dma_desc_enable || in dwc2_hcd_init()
5252 hsotg->params.dma_desc_fs_enable) { in dwc2_hcd_init()
5253 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", in dwc2_hcd_init()
5257 if (!hsotg->desc_gen_cache) { in dwc2_hcd_init()
5258 dev_err(hsotg->dev, in dwc2_hcd_init()
5262 * Disable descriptor dma mode since it will not be in dwc2_hcd_init()
5265 hsotg->params.dma_desc_enable = false; in dwc2_hcd_init()
5266 hsotg->params.dma_desc_fs_enable = false; in dwc2_hcd_init()
5269 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", in dwc2_hcd_init()
5272 if (!hsotg->desc_hsisoc_cache) { in dwc2_hcd_init()
5273 dev_err(hsotg->dev, in dwc2_hcd_init()
5276 kmem_cache_destroy(hsotg->desc_gen_cache); in dwc2_hcd_init()
5279 * Disable descriptor dma mode since it will not be in dwc2_hcd_init()
5282 hsotg->params.dma_desc_enable = false; in dwc2_hcd_init()
5283 hsotg->params.dma_desc_fs_enable = false; in dwc2_hcd_init()
5287 if (hsotg->params.host_dma) { in dwc2_hcd_init()
5289 * Create kmem caches to handle non-aligned buffer in dwc2_hcd_init()
5290 * in Buffer DMA mode. in dwc2_hcd_init()
5292 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma", in dwc2_hcd_init()
5295 if (!hsotg->unaligned_cache) in dwc2_hcd_init()
5296 dev_err(hsotg->dev, in dwc2_hcd_init()
5300 hsotg->otg_port = 1; in dwc2_hcd_init()
5301 hsotg->frame_list = NULL; in dwc2_hcd_init()
5302 hsotg->frame_list_dma = 0; in dwc2_hcd_init()
5303 hsotg->periodic_qh_count = 0; in dwc2_hcd_init()
5306 hsotg->lx_state = DWC2_L3; in dwc2_hcd_init()
5308 hcd->self.otg_port = hsotg->otg_port; in dwc2_hcd_init()
5311 hcd->self.sg_tablesize = 0; in dwc2_hcd_init()
5313 hcd->tpl_support = of_usb_host_tpl_support(hsotg->dev->of_node); in dwc2_hcd_init()
5315 if (!IS_ERR_OR_NULL(hsotg->uphy)) in dwc2_hcd_init()
5316 otg_set_host(hsotg->uphy->otg, &hcd->self); in dwc2_hcd_init()
5323 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); in dwc2_hcd_init()
5327 device_wakeup_enable(hcd->self.controller); in dwc2_hcd_init()
5336 kmem_cache_destroy(hsotg->unaligned_cache); in dwc2_hcd_init()
5337 kmem_cache_destroy(hsotg->desc_hsisoc_cache); in dwc2_hcd_init()
5338 kmem_cache_destroy(hsotg->desc_gen_cache); in dwc2_hcd_init()
5346 kfree(hsotg->last_frame_num_array); in dwc2_hcd_init()
5347 kfree(hsotg->frame_num_array); in dwc2_hcd_init()
5350 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); in dwc2_hcd_init()
5362 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); in dwc2_hcd_remove()
5365 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); in dwc2_hcd_remove()
5368 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", in dwc2_hcd_remove()
5373 if (!IS_ERR_OR_NULL(hsotg->uphy)) in dwc2_hcd_remove()
5374 otg_set_host(hsotg->uphy->otg, NULL); in dwc2_hcd_remove()
5377 hsotg->priv = NULL; in dwc2_hcd_remove()
5379 kmem_cache_destroy(hsotg->unaligned_cache); in dwc2_hcd_remove()
5380 kmem_cache_destroy(hsotg->desc_hsisoc_cache); in dwc2_hcd_remove()
5381 kmem_cache_destroy(hsotg->desc_gen_cache); in dwc2_hcd_remove()
5387 kfree(hsotg->last_frame_num_array); in dwc2_hcd_remove()
5388 kfree(hsotg->frame_num_array); in dwc2_hcd_remove()
5393 * dwc2_backup_host_registers() - Backup controller host registers.
5404 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_host_registers()
5407 hr = &hsotg->hr_backup; in dwc2_backup_host_registers()
5408 hr->hcfg = dwc2_readl(hsotg, HCFG); in dwc2_backup_host_registers()
5409 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK); in dwc2_backup_host_registers()
5410 for (i = 0; i < hsotg->params.host_channels; ++i) in dwc2_backup_host_registers()
5411 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i)); in dwc2_backup_host_registers()
5413 hr->hprt0 = dwc2_read_hprt0(hsotg); in dwc2_backup_host_registers()
5414 hr->hfir = dwc2_readl(hsotg, HFIR); in dwc2_backup_host_registers()
5415 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); in dwc2_backup_host_registers()
5416 hr->valid = true; in dwc2_backup_host_registers()
5422 * dwc2_restore_host_registers() - Restore controller host registers.
5433 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_host_registers()
5436 hr = &hsotg->hr_backup; in dwc2_restore_host_registers()
5437 if (!hr->valid) { in dwc2_restore_host_registers()
5438 dev_err(hsotg->dev, "%s: no host registers to restore\n", in dwc2_restore_host_registers()
5440 return -EINVAL; in dwc2_restore_host_registers()
5442 hr->valid = false; in dwc2_restore_host_registers()
5444 dwc2_writel(hsotg, hr->hcfg, HCFG); in dwc2_restore_host_registers()
5445 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK); in dwc2_restore_host_registers()
5447 for (i = 0; i < hsotg->params.host_channels; ++i) in dwc2_restore_host_registers()
5448 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i)); in dwc2_restore_host_registers()
5450 dwc2_writel(hsotg, hr->hprt0, HPRT0); in dwc2_restore_host_registers()
5451 dwc2_writel(hsotg, hr->hfir, HFIR); in dwc2_restore_host_registers()
5452 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ); in dwc2_restore_host_registers()
5453 hsotg->frame_number = 0; in dwc2_restore_host_registers()
5459 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5472 dev_dbg(hsotg->dev, "Preparing host for hibernation\n"); in dwc2_host_enter_hibernation()
5475 dev_err(hsotg->dev, "%s: failed to backup global registers\n", in dwc2_host_enter_hibernation()
5481 dev_err(hsotg->dev, "%s: failed to backup host registers\n", in dwc2_host_enter_hibernation()
5486 /* Enter USB Suspend Mode */ in dwc2_host_enter_hibernation()
5494 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); in dwc2_host_enter_hibernation()
5497 * We need to disable interrupts to prevent servicing of any IRQ in dwc2_host_enter_hibernation()
5498 * during going to hibernation in dwc2_host_enter_hibernation()
5500 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_host_enter_hibernation()
5501 hsotg->lx_state = DWC2_L2; in dwc2_host_enter_hibernation()
5535 /* Unmask host mode interrupts in GPWRDN */ in dwc2_host_enter_hibernation()
5554 hsotg->hibernated = 1; in dwc2_host_enter_hibernation()
5555 hsotg->bus_suspended = 1; in dwc2_host_enter_hibernation()
5556 dev_dbg(hsotg->dev, "Host hibernation completed\n"); in dwc2_host_enter_hibernation()
5557 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_host_enter_hibernation()
5568 * Return: non-zero if failed to enter to hibernation.
5570 * This function is for exiting from Host mode hibernation by
5571 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5582 gr = &hsotg->gr_backup; in dwc2_host_exit_hibernation()
5583 hr = &hsotg->hr_backup; in dwc2_host_exit_hibernation()
5585 dev_dbg(hsotg->dev, in dwc2_host_exit_hibernation()
5590 hsotg->hibernated = 0; in dwc2_host_exit_hibernation()
5595 * core is in Device mode(gintsts.curmode == 0) in dwc2_host_exit_hibernation()
5602 /* De-assert Restore */ in dwc2_host_exit_hibernation()
5609 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); in dwc2_host_exit_hibernation()
5610 dwc2_writel(hsotg, hr->hcfg, HCFG); in dwc2_host_exit_hibernation()
5612 /* De-assert Wakeup Logic */ in dwc2_host_exit_hibernation()
5618 hprt0 = hr->hprt0; in dwc2_host_exit_hibernation()
5624 hprt0 = hr->hprt0; in dwc2_host_exit_hibernation()
5661 dev_err(hsotg->dev, "%s: failed to restore registers\n", in dwc2_host_exit_hibernation()
5669 dev_err(hsotg->dev, "%s: failed to restore host registers\n", in dwc2_host_exit_hibernation()
5677 * Change "port_connect_status_change" flag to re-enumerate, in dwc2_host_exit_hibernation()
5678 * because after exit from hibernation port connection status in dwc2_host_exit_hibernation()
5681 hsotg->flags.b.port_connect_status_change = 1; in dwc2_host_exit_hibernation()
5684 hsotg->hibernated = 0; in dwc2_host_exit_hibernation()
5685 hsotg->bus_suspended = 0; in dwc2_host_exit_hibernation()
5686 hsotg->lx_state = DWC2_L0; in dwc2_host_exit_hibernation()
5687 dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); in dwc2_host_exit_hibernation()
5693 struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub; in dwc2_host_can_poweroff_phy()
5696 if (!device_may_wakeup(dwc2->dev)) in dwc2_host_can_poweroff_phy()
5711 * dwc2_host_enter_partial_power_down() - Put controller in partial
5716 * Return: non-zero if failed to enter host partial power down.
5718 * This function is for entering Host mode partial power down.
5726 dev_dbg(hsotg->dev, "Entering host partial power down started.\n"); in dwc2_host_enter_partial_power_down()
5728 /* Put this port in suspend mode. */ in dwc2_host_enter_partial_power_down()
5736 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); in dwc2_host_enter_partial_power_down()
5741 dev_err(hsotg->dev, "%s: failed to backup global registers\n", in dwc2_host_enter_partial_power_down()
5748 dev_err(hsotg->dev, "%s: failed to backup host registers\n", in dwc2_host_enter_partial_power_down()
5774 hsotg->in_ppd = 1; in dwc2_host_enter_partial_power_down()
5775 hsotg->lx_state = DWC2_L2; in dwc2_host_enter_partial_power_down()
5776 hsotg->bus_suspended = true; in dwc2_host_enter_partial_power_down()
5778 dev_dbg(hsotg->dev, "Entering host partial power down completed.\n"); in dwc2_host_enter_partial_power_down()
5784 * dwc2_host_exit_partial_power_down() - Exit controller from host partial
5791 * Return: non-zero if failed to exit host partial power down.
5793 * This function is for exiting from Host mode partial power down.
5802 dev_dbg(hsotg->dev, "Exiting host partial power down started.\n"); in dwc2_host_exit_partial_power_down()
5822 dev_err(hsotg->dev, "%s: failed to restore registers\n", in dwc2_host_exit_partial_power_down()
5829 dev_err(hsotg->dev, "%s: failed to restore host registers\n", in dwc2_host_exit_partial_power_down()
5835 /* Drive resume signaling and exit suspend mode on the port. */ in dwc2_host_exit_partial_power_down()
5848 hsotg->bus_suspended = false; in dwc2_host_exit_partial_power_down()
5858 mod_timer(&hsotg->wkp_timer, in dwc2_host_exit_partial_power_down()
5863 hsotg->in_ppd = 0; in dwc2_host_exit_partial_power_down()
5864 hsotg->lx_state = DWC2_L0; in dwc2_host_exit_partial_power_down()
5866 dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n"); in dwc2_host_exit_partial_power_down()
5871 * dwc2_host_enter_clock_gating() - Put controller in clock gating.
5875 * This function is for entering Host mode clock gating.
5882 dev_dbg(hsotg->dev, "Entering host clock gating.\n"); in dwc2_host_enter_clock_gating()
5884 /* Put this port in suspend mode. */ in dwc2_host_enter_clock_gating()
5901 hsotg->bus_suspended = true; in dwc2_host_enter_clock_gating()
5902 hsotg->lx_state = DWC2_L2; in dwc2_host_enter_clock_gating()
5906 * dwc2_host_exit_clock_gating() - Exit controller from clock gating.
5911 * This function is for exiting Host mode clock gating.
5918 dev_dbg(hsotg->dev, "Exiting host clock gating.\n"); in dwc2_host_exit_clock_gating()
5932 /* Drive resume signaling and exit suspend mode on the port. */ in dwc2_host_exit_clock_gating()
5948 hsotg->bus_suspended = false; in dwc2_host_exit_clock_gating()
5949 hsotg->lx_state = DWC2_L0; in dwc2_host_exit_clock_gating()
5951 mod_timer(&hsotg->wkp_timer, in dwc2_host_exit_clock_gating()