1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Copyright (C) 2011-2013 Samsung India Software Operations
17 #include "ufshcd-pltfrm.h"
27 	struct device *dev = hba->dev;  in ufshcd_parse_clock_info()
28 	struct device_node *np = dev->of_node;  in ufshcd_parse_clock_info()
38 	cnt = of_property_count_strings(np, "clock-names");  in ufshcd_parse_clock_info()
39 	if (!cnt || (cnt == -EINVAL)) {  in ufshcd_parse_clock_info()
51 	if (!of_get_property(np, "freq-table-hz", &len)) {  in ufshcd_parse_clock_info()
52 		dev_info(dev, "freq-table-hz property not specified\n");  in ufshcd_parse_clock_info()
61 		dev_err(dev, "%s len mismatch\n", "freq-table-hz");  in ufshcd_parse_clock_info()
62 		ret = -EINVAL;  in ufshcd_parse_clock_info()
69 		ret = -ENOMEM;  in ufshcd_parse_clock_info()
73 	ret = of_property_read_u32_array(np, "freq-table-hz",  in ufshcd_parse_clock_info()
75 	if (ret && (ret != -EINVAL)) {  in ufshcd_parse_clock_info()
77 				"freq-table-hz", ret);  in ufshcd_parse_clock_info()
82 		ret = of_property_read_string_index(np,	"clock-names", i/2,  in ufshcd_parse_clock_info()
89 			ret = -ENOMEM;  in ufshcd_parse_clock_info()
93 		clki->min_freq = clkfreq[i];  in ufshcd_parse_clock_info()
94 		clki->max_freq = clkfreq[i+1];  in ufshcd_parse_clock_info()
95 		clki->name = devm_kstrdup(dev, name, GFP_KERNEL);  in ufshcd_parse_clock_info()
96 		if (!clki->name) {  in ufshcd_parse_clock_info()
97 			ret = -ENOMEM;  in ufshcd_parse_clock_info()
102 			clki->keep_link_active = true;  in ufshcd_parse_clock_info()
103 		dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",  in ufshcd_parse_clock_info()
104 				clki->min_freq, clki->max_freq, clki->name);  in ufshcd_parse_clock_info()
105 		list_add_tail(&clki->list, &hba->clk_list_head);  in ufshcd_parse_clock_info()
128 	struct device_node *np = dev->of_node;  in ufshcd_populate_vreg()
135 	snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);  in ufshcd_populate_vreg()
144 		return -ENOMEM;  in ufshcd_populate_vreg()
146 	vreg->name = devm_kstrdup(dev, name, GFP_KERNEL);  in ufshcd_populate_vreg()
147 	if (!vreg->name)  in ufshcd_populate_vreg()
148 		return -ENOMEM;  in ufshcd_populate_vreg()
150 	snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);  in ufshcd_populate_vreg()
151 	if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {  in ufshcd_populate_vreg()
153 		vreg->max_uA = 0;  in ufshcd_populate_vreg()
162  * ufshcd_parse_regulator_info - get regulator info from device tree
165  * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
166  * If any of the supplies are not defined it is assumed that they are always-on
173 	struct device *dev = hba->dev;  in ufshcd_parse_regulator_info()
174 	struct ufs_vreg_info *info = &hba->vreg_info;  in ufshcd_parse_regulator_info()
176 	err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);  in ufshcd_parse_regulator_info()
180 	err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);  in ufshcd_parse_regulator_info()
184 	err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);  in ufshcd_parse_regulator_info()
188 	err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);  in ufshcd_parse_regulator_info()
201 	struct device *dev = hba->dev;  in ufshcd_init_lanes_per_dir()
204 	ret = of_property_read_u32(dev->of_node, "lanes-per-direction",  in ufshcd_init_lanes_per_dir()
205 		&hba->lanes_per_direction);  in ufshcd_init_lanes_per_dir()
207 		dev_dbg(hba->dev,  in ufshcd_init_lanes_per_dir()
208 			"%s: failed to read lanes-per-direction, ret=%d\n",  in ufshcd_init_lanes_per_dir()
210 		hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;  in ufshcd_init_lanes_per_dir()
215  * ufshcd_get_pwr_dev_param - get finally agreed attributes for
221  * Returns 0 on success, non-zero value on failure
232 	if (dev_max->pwr_rx == FAST_MODE)  in ufshcd_get_pwr_dev_param()
235 	if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {  in ufshcd_get_pwr_dev_param()
237 		min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,  in ufshcd_get_pwr_dev_param()
238 					pltfrm_param->hs_tx_gear);  in ufshcd_get_pwr_dev_param()
240 		min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,  in ufshcd_get_pwr_dev_param()
241 					pltfrm_param->pwm_tx_gear);  in ufshcd_get_pwr_dev_param()
246 	 * pltfrm_param->desired_working_mode is HS,  in ufshcd_get_pwr_dev_param()
252 		return -ENOTSUPP;  in ufshcd_get_pwr_dev_param()
256 		 * since pltfrm_param->desired_working_mode is also HS  in ufshcd_get_pwr_dev_param()
260 		agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;  in ufshcd_get_pwr_dev_param()
261 		agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;  in ufshcd_get_pwr_dev_param()
264 		 * here pltfrm_param->desired_working_mode is PWM.  in ufshcd_get_pwr_dev_param()
266 		 * in both cases pltfrm_param->desired_working_mode will  in ufshcd_get_pwr_dev_param()
269 		agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;  in ufshcd_get_pwr_dev_param()
270 		agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;  in ufshcd_get_pwr_dev_param()
278 	agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,  in ufshcd_get_pwr_dev_param()
279 				    pltfrm_param->tx_lanes);  in ufshcd_get_pwr_dev_param()
280 	agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,  in ufshcd_get_pwr_dev_param()
281 				    pltfrm_param->rx_lanes);  in ufshcd_get_pwr_dev_param()
284 	min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);  in ufshcd_get_pwr_dev_param()
287 	 * if both device capabilities and vendor pre-defined preferences are  in ufshcd_get_pwr_dev_param()
296 		agreed_pwr->gear_rx =  in ufshcd_get_pwr_dev_param()
299 		agreed_pwr->gear_rx = min_dev_gear;  in ufshcd_get_pwr_dev_param()
301 		agreed_pwr->gear_rx = min_pltfrm_gear;  in ufshcd_get_pwr_dev_param()
303 	agreed_pwr->gear_tx = agreed_pwr->gear_rx;  in ufshcd_get_pwr_dev_param()
305 	agreed_pwr->hs_rate = pltfrm_param->hs_rate;  in ufshcd_get_pwr_dev_param()
331  * ufshcd_pltfrm_init - probe routine of the driver
335  * Returns 0 on success, non-zero value on failure
343 	struct device *dev = &pdev->dev;  in ufshcd_pltfrm_init()
363 	hba->vops = vops;  in ufshcd_pltfrm_init()