Lines Matching +full:fsd +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
11 #include <linux/clk.h>
22 #include "ufshcd-pltfrm.h"
26 #include "ufs-exynos.h"
88 /* Multi-host registers */
198 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynosauto_ufs_drv_init()
201 if (ufs->sysreg) { in exynosauto_ufs_drv_init()
202 return regmap_update_bits(ufs->sysreg, in exynosauto_ufs_drv_init()
203 ufs->shareability_reg_offset, in exynosauto_ufs_drv_init()
207 attr->tx_dif_p_nsec = 3200000; in exynosauto_ufs_drv_init()
214 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
228 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
232 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
233 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
238 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
255 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
283 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
296 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
309 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
310 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite; in exynos7_ufs_pre_link()
339 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
369 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
370 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); in exynos7_ufs_post_pwr_change()
384 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
386 * - Before host controller S/W reset
387 * - Access to UFS protector's register
415 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
416 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
427 if (!IS_ERR(clki->clk)) { in exynos_ufs_get_clk_info()
428 if (!strcmp(clki->name, "core_clk")) in exynos_ufs_get_clk_info()
429 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
430 else if (!strcmp(clki->name, "sclk_unipro_main")) in exynos_ufs_get_clk_info()
431 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
435 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
436 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
437 ret = -EINVAL; in exynos_ufs_get_clk_info()
441 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
442 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
443 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
444 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
446 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
457 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
458 ret = -EINVAL; in exynos_ufs_get_clk_info()
462 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
463 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
471 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
475 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
482 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
483 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
486 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); in exynos_ufs_set_pwm_clk_div()
491 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
492 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
497 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
498 int i = 0, clk_idx = -1; in exynos_ufs_calc_pwm_clk_div()
504 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
506 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
511 if (clk_idx == -1) { in exynos_ufs_calc_pwm_clk_div()
513 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
517 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; in exynos_ufs_calc_pwm_clk_div()
523 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
534 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
535 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
537 t_cfg->tx_linereset_p = in exynos_ufs_specify_phy_time_attr()
538 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
539 t_cfg->tx_linereset_n = in exynos_ufs_specify_phy_time_attr()
540 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
541 t_cfg->tx_high_z_cnt = in exynos_ufs_specify_phy_time_attr()
542 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
543 t_cfg->tx_base_n_val = in exynos_ufs_specify_phy_time_attr()
544 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
545 t_cfg->tx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
546 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
547 t_cfg->tx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
548 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
550 t_cfg->rx_linereset = in exynos_ufs_specify_phy_time_attr()
551 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
552 t_cfg->rx_hibern8_wait = in exynos_ufs_specify_phy_time_attr()
553 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
554 t_cfg->rx_base_n_val = in exynos_ufs_specify_phy_time_attr()
555 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
556 t_cfg->rx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
557 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
558 t_cfg->rx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
559 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
560 t_cfg->rx_stall_cnt = in exynos_ufs_specify_phy_time_attr()
561 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
566 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
567 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
576 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
578 RX_LINERESET(t_cfg->rx_linereset)); in exynos_ufs_config_phy_time_attr()
580 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
582 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
584 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
586 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
588 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
590 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); in exynos_ufs_config_phy_time_attr()
595 TX_LINERESET_P(t_cfg->tx_linereset_p)); in exynos_ufs_config_phy_time_attr()
597 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
599 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
601 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
603 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
605 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
607 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
610 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
612 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
620 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
621 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
629 attr->rx_hs_g1_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
632 attr->rx_hs_g2_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
635 attr->rx_hs_g3_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
638 attr->rx_hs_g1_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
641 attr->rx_hs_g2_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
644 attr->rx_hs_g3_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
647 if (attr->rx_adv_fine_gran_sup_en == 0) { in exynos_ufs_config_phy_cap_attr()
652 if (attr->rx_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
656 attr->rx_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
658 if (attr->rx_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
661 attr->rx_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
663 } else if (attr->rx_adv_fine_gran_sup_en == 1) { in exynos_ufs_config_phy_cap_attr()
665 if (attr->rx_adv_fine_gran_step) in exynos_ufs_config_phy_cap_attr()
669 attr->rx_adv_fine_gran_step)); in exynos_ufs_config_phy_cap_attr()
671 if (attr->rx_adv_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
675 attr->rx_adv_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
677 if (attr->rx_adv_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
681 attr->rx_adv_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
690 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
731 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
732 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); in exynos_ufs_config_sync_pattern_mask()
767 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
773 ret = -EINVAL; in exynos_ufs_pre_pwr_mode()
786 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
787 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
792 switch (dev_req_params->hs_rate) { in exynos_ufs_pre_pwr_mode()
815 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
816 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); in exynos_ufs_post_pwr_mode()
817 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); in exynos_ufs_post_pwr_mode()
827 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
828 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
831 switch (pwr_req->hs_rate) { in exynos_ufs_post_pwr_mode()
839 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", in exynos_ufs_post_pwr_mode()
846 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
889 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
890 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
893 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
895 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
897 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
898 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
900 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
903 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
906 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
925 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
928 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
930 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
932 ufs->drv_data->uic_attr->pa_dbg_option_suite); in exynos_ufs_config_unipro()
965 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
970 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
990 /* m-phy */ in exynos_ufs_pre_link()
992 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
999 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
1000 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1016 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1017 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1025 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1026 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1029 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1033 if (attr->pa_granularity) { in exynos_ufs_post_link()
1036 attr->pa_granularity); in exynos_ufs_post_link()
1039 if (attr->pa_tactivate) in exynos_ufs_post_link()
1041 attr->pa_tactivate); in exynos_ufs_post_link()
1042 if (attr->pa_hibern8time && in exynos_ufs_post_link()
1043 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1045 attr->pa_hibern8time); in exynos_ufs_post_link()
1048 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1049 if (!attr->pa_granularity) in exynos_ufs_post_link()
1051 &attr->pa_granularity); in exynos_ufs_post_link()
1052 if (!attr->pa_hibern8time) in exynos_ufs_post_link()
1054 &attr->pa_hibern8time); in exynos_ufs_post_link()
1060 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { in exynos_ufs_post_link()
1062 dev_warn(hba->dev, in exynos_ufs_post_link()
1065 attr->pa_granularity); in exynos_ufs_post_link()
1066 attr->pa_granularity = 6; in exynos_ufs_post_link()
1072 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1073 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1080 struct device_node *np = dev->of_node; in exynos_ufs_parse_dt()
1084 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1086 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1087 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1090 ret = -EINVAL; in exynos_ufs_parse_dt()
1094 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1095 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1096 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1099 &ufs->shareability_reg_offset)) { in exynos_ufs_parse_dt()
1101 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1105 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1106 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1108 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; in exynos_ufs_parse_dt()
1109 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; in exynos_ufs_parse_dt()
1110 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; in exynos_ufs_parse_dt()
1111 attr->pa_granularity = PA_GRANULARITY_VAL; in exynos_ufs_parse_dt()
1112 attr->pa_tactivate = PA_TACTIVATE_VAL; in exynos_ufs_parse_dt()
1113 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; in exynos_ufs_parse_dt()
1122 ufs->hba = hba; in exynos_ufs_priv_init()
1123 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1124 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1125 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1126 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1127 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1128 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1133 struct device *dev = hba->dev; in exynos_ufs_init()
1140 return -ENOMEM; in exynos_ufs_init()
1142 /* exynos-specific hci */ in exynos_ufs_init()
1143 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1144 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1146 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1150 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1151 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1153 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1157 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1158 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1160 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1169 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1170 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1171 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1172 dev_err(dev, "failed to get ufs-phy\n"); in exynos_ufs_init()
1178 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1179 ret = ufs->drv_data->drv_init(dev, ufs); in exynos_ufs_init()
1181 dev_err(dev, "failed to init drv-data\n"); in exynos_ufs_init()
1194 hba->priv = NULL; in exynos_ufs_init()
1214 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1215 ret = -ETIMEDOUT; in exynos_ufs_host_reset()
1234 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1237 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1241 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1245 int h8_time = attr->pa_hibern8time * in exynos_ufs_pre_hibern8()
1246 granularity_tbl[attr->pa_granularity - 1]; in exynos_ufs_pre_hibern8()
1251 delta = h8_time - ktime_us_delta(ktime_get(), in exynos_ufs_pre_hibern8()
1252 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1272 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) in exynos_ufs_post_hibern8()
1279 dev_warn(hba->dev, "%s: power mode change\n", __func__); in exynos_ufs_post_hibern8()
1280 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; in exynos_ufs_post_hibern8()
1281 hba->pwr_info.pwr_tx = cur_mode & 0xf; in exynos_ufs_post_hibern8()
1282 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); in exynos_ufs_post_hibern8()
1285 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) in exynos_ufs_post_hibern8()
1288 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1290 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1303 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1304 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1316 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1319 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1320 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1388 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1398 phy_power_on(ufs->phy); in exynos_ufs_resume()
1435 return -ETIME; in exynosauto_ufs_vh_wait_ph_ready()
1440 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1447 return -ENOMEM; in exynosauto_ufs_vh_init()
1449 /* exynos-specific hci */ in exynosauto_ufs_vh_init()
1450 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1451 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1453 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1460 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1461 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1462 return -ENODEV; in exynosauto_ufs_vh_init()
1472 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link()
1475 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1481 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1487 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1509 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link()
1547 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change()
1585 struct device *dev = &pdev->dev; in exynos_ufs_probe()
1590 if (drv_data && drv_data->vops) in exynos_ufs_probe()
1591 vops = drv_data->vops; in exynos_ufs_probe()
1605 pm_runtime_get_sync(&(pdev)->dev); in exynos_ufs_remove()
1608 phy_power_off(ufs->phy); in exynos_ufs_remove()
1609 phy_exit(ufs->phy); in exynos_ufs_remove()
1731 { .compatible = "samsung,exynos7-ufs",
1733 { .compatible = "samsung,exynosautov9-ufs",
1735 { .compatible = "samsung,exynosautov9-ufs-vh",
1737 { .compatible = "tesla,fsd-ufs",
1754 .name = "exynos-ufshc",