Lines Matching +full:0 +full:x08
11 u8 rfifo[0x20]; /* Receive FIFO */
24 u8 ccr0; /* Channel Configuration Register 0 */
33 u8 isr0; /* Interrupt Status 0 */
42 u8 xfifo[0x20]; /* Transmit FIFO */
69 u8 imr0; /* Interrupt Mask Register 0 */
78 u8 __pad1[0x20];
128 #define SAB82532_ALLS 0x00000001
129 #define SAB82532_XPR 0x00000002
130 #define SAB82532_REGS_PENDING 0x00000004
133 #define SAB82532_RSTAT_PE 0x80
134 #define SAB82532_RSTAT_FE 0x40
135 #define SAB82532_RSTAT_PARITY 0x01
138 #define SAB82532_STAR_XDOV 0x80
139 #define SAB82532_STAR_XFW 0x40
140 #define SAB82532_STAR_RFNE 0x20
141 #define SAB82532_STAR_FCS 0x10
142 #define SAB82532_STAR_TEC 0x08
143 #define SAB82532_STAR_CEC 0x04
144 #define SAB82532_STAR_CTS 0x02
147 #define SAB82532_CMDR_RMC 0x80
148 #define SAB82532_CMDR_RRES 0x40
149 #define SAB82532_CMDR_RFRD 0x20
150 #define SAB82532_CMDR_STI 0x10
151 #define SAB82532_CMDR_XF 0x08
152 #define SAB82532_CMDR_XRES 0x01
155 #define SAB82532_MODE_FRTS 0x40
156 #define SAB82532_MODE_FCTS 0x20
157 #define SAB82532_MODE_FLON 0x10
158 #define SAB82532_MODE_RAC 0x08
159 #define SAB82532_MODE_RTS 0x04
160 #define SAB82532_MODE_TRS 0x02
161 #define SAB82532_MODE_TLP 0x01
164 #define SAB82532_TIMR_CNT_MASK 0xe0
165 #define SAB82532_TIMR_VALUE_MASK 0x1f
168 #define SAB82532_DAFO_XBRK 0x40
169 #define SAB82532_DAFO_STOP 0x20
170 #define SAB82532_DAFO_PAR_SPACE 0x00
171 #define SAB82532_DAFO_PAR_ODD 0x08
172 #define SAB82532_DAFO_PAR_EVEN 0x10
173 #define SAB82532_DAFO_PAR_MARK 0x18
174 #define SAB82532_DAFO_PARE 0x04
175 #define SAB82532_DAFO_CHL8 0x00
176 #define SAB82532_DAFO_CHL7 0x01
177 #define SAB82532_DAFO_CHL6 0x02
178 #define SAB82532_DAFO_CHL5 0x03
181 #define SAB82532_RFC_DPS 0x40
182 #define SAB82532_RFC_DXS 0x20
183 #define SAB82532_RFC_RFDF 0x10
184 #define SAB82532_RFC_RFTH_1 0x00
185 #define SAB82532_RFC_RFTH_4 0x04
186 #define SAB82532_RFC_RFTH_16 0x08
187 #define SAB82532_RFC_RFTH_32 0x0c
188 #define SAB82532_RFC_TCDE 0x01
191 #define SAB82532_RBCH_DMA 0x80
192 #define SAB82532_RBCH_CAS 0x20
195 #define SAB82532_XBCH_DMA 0x80
196 #define SAB82532_XBCH_CAS 0x20
197 #define SAB82532_XBCH_XC 0x10
199 /* Channel Configuration Register 0 (CCR0) */
200 #define SAB82532_CCR0_PU 0x80
201 #define SAB82532_CCR0_MCE 0x40
202 #define SAB82532_CCR0_SC_NRZ 0x00
203 #define SAB82532_CCR0_SC_NRZI 0x08
204 #define SAB82532_CCR0_SC_FM0 0x10
205 #define SAB82532_CCR0_SC_FM1 0x14
206 #define SAB82532_CCR0_SC_MANCH 0x18
207 #define SAB82532_CCR0_SM_HDLC 0x00
208 #define SAB82532_CCR0_SM_SDLC_LOOP 0x01
209 #define SAB82532_CCR0_SM_BISYNC 0x02
210 #define SAB82532_CCR0_SM_ASYNC 0x03
213 #define SAB82532_CCR1_ODS 0x10
214 #define SAB82532_CCR1_BCR 0x08
215 #define SAB82532_CCR1_CM_MASK 0x07
218 #define SAB82532_CCR2_SOC1 0x80
219 #define SAB82532_CCR2_SOC0 0x40
220 #define SAB82532_CCR2_BR9 0x80
221 #define SAB82532_CCR2_BR8 0x40
222 #define SAB82532_CCR2_BDF 0x20
223 #define SAB82532_CCR2_SSEL 0x10
224 #define SAB82532_CCR2_XCS0 0x20
225 #define SAB82532_CCR2_RCS0 0x10
226 #define SAB82532_CCR2_TOE 0x08
227 #define SAB82532_CCR2_RWX 0x04
228 #define SAB82532_CCR2_DIV 0x01
231 #define SAB82532_CCR3_PSD 0x01
234 #define SAB82532_TSAX_TSNX_MASK 0xfc
235 #define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
236 #define SAB82532_TSAX_XCS1 0x01
239 #define SAB82532_TSAR_TSNR_MASK 0xfc
240 #define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
241 #define SAB82532_TSAR_RCS1 0x01
244 #define SAB82532_VSTR_CD 0x80
245 #define SAB82532_VSTR_DPLA 0x40
246 #define SAB82532_VSTR_VN_MASK 0x0f
247 #define SAB82532_VSTR_VN_1 0x00
248 #define SAB82532_VSTR_VN_2 0x01
249 #define SAB82532_VSTR_VN_3_2 0x02
252 #define SAB82532_GIS_PI 0x80
253 #define SAB82532_GIS_ISA1 0x08
254 #define SAB82532_GIS_ISA0 0x04
255 #define SAB82532_GIS_ISB1 0x02
256 #define SAB82532_GIS_ISB0 0x01
259 #define SAB82532_IVA_MASK 0xf1
262 #define SAB82532_IPC_VIS 0x80
263 #define SAB82532_IPC_SLA1 0x10
264 #define SAB82532_IPC_SLA0 0x08
265 #define SAB82532_IPC_CASM 0x04
266 #define SAB82532_IPC_IC_OPEN_DRAIN 0x00
267 #define SAB82532_IPC_IC_ACT_LOW 0x01
268 #define SAB82532_IPC_IC_ACT_HIGH 0x03
270 /* Interrupt Status Register 0 (ISR0) */
271 #define SAB82532_ISR0_TCD 0x80
272 #define SAB82532_ISR0_TIME 0x40
273 #define SAB82532_ISR0_PERR 0x20
274 #define SAB82532_ISR0_FERR 0x10
275 #define SAB82532_ISR0_PLLA 0x08
276 #define SAB82532_ISR0_CDSC 0x04
277 #define SAB82532_ISR0_RFO 0x02
278 #define SAB82532_ISR0_RPF 0x01
281 #define SAB82532_ISR1_BRK 0x80
282 #define SAB82532_ISR1_BRKT 0x40
283 #define SAB82532_ISR1_ALLS 0x20
284 #define SAB82532_ISR1_XOFF 0x10
285 #define SAB82532_ISR1_TIN 0x08
286 #define SAB82532_ISR1_CSC 0x04
287 #define SAB82532_ISR1_XON 0x02
288 #define SAB82532_ISR1_XPR 0x01
290 /* Interrupt Mask Register 0 (IMR0) */
291 #define SAB82532_IMR0_TCD 0x80
292 #define SAB82532_IMR0_TIME 0x40
293 #define SAB82532_IMR0_PERR 0x20
294 #define SAB82532_IMR0_FERR 0x10
295 #define SAB82532_IMR0_PLLA 0x08
296 #define SAB82532_IMR0_CDSC 0x04
297 #define SAB82532_IMR0_RFO 0x02
298 #define SAB82532_IMR0_RPF 0x01
301 #define SAB82532_IMR1_BRK 0x80
302 #define SAB82532_IMR1_BRKT 0x40
303 #define SAB82532_IMR1_ALLS 0x20
304 #define SAB82532_IMR1_XOFF 0x10
305 #define SAB82532_IMR1_TIN 0x08
306 #define SAB82532_IMR1_CSC 0x04
307 #define SAB82532_IMR1_XON 0x02
308 #define SAB82532_IMR1_XPR 0x01
311 #define SAB82532_PIS_SYNC_B 0x08
312 #define SAB82532_PIS_DTR_B 0x04
313 #define SAB82532_PIS_DTR_A 0x02
314 #define SAB82532_PIS_SYNC_A 0x01
317 #define SAB82532_CCR4_MCK4 0x80
318 #define SAB82532_CCR4_EBRG 0x40
319 #define SAB82532_CCR4_TST1 0x20
320 #define SAB82532_CCR4_ICD 0x10