1 // SPDX-License-Identifier: GPL-2.0+
3  * SiFive UART driver
5  * Copyright (C) 2018-2019 SiFive
8  * - drivers/tty/serial/pxa.c
9  * - drivers/tty/serial/amba-pl011.c
10  * - drivers/tty/serial/uartlite.c
11  * - drivers/tty/serial/omap-serial.c
12  * - drivers/pwm/pwm-sifive.c
15  * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16  *   SiFive FE310-G000 v2p3
17  * - The tree/master/src/main/scala/devices/uart directory of
18  *   https://github.com/sifive/sifive-blocks/
20  * The SiFive UART design is not 8250-compatible.  The following common
22  * - Word lengths other than 8 bits
23  * - Break handling
24  * - Parity
25  * - Flow control
26  * - Modem signals (DSR, RI, etc.)
117 #define SIFIVE_SERIAL_NAME			"sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
137  * struct sifive_serial_port - driver-specific data extension to struct uart_port
145  * Configuration data specific to this SiFive UART.
157  * Structure container-of macros
178  * __ssp_early_writel() - write to a SiFive serial port register (early)
191 	writel_relaxed(v, port->membase + offs);  in __ssp_early_writel()
195  * __ssp_early_readl() - read from a SiFive serial port register (early)
211 	return readl_relaxed(port->membase + offs);  in __ssp_early_readl()
215  * __ssp_writel() - write to a SiFive serial port register
227 	__ssp_early_writel(v, offs, &ssp->port);  in __ssp_writel()
231  * __ssp_readl() - read from a SiFive serial port register
244 	return __ssp_early_readl(&ssp->port, offs);  in __ssp_readl()
248  * sifive_serial_is_txfifo_full() - is the TXFIFO full?
251  * Read the transmit FIFO "full" bit, returning a non-zero value if the
255  * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
265  * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
281  * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
285  * transmit buffer to the SiFive UART TX FIFO.
287  * Context: Any context.  Expects @ssp->port.lock to be held by caller.
291 	struct circ_buf *xmit = &ssp->port.state->xmit;  in __ssp_transmit_chars()
294 	if (ssp->port.x_char) {  in __ssp_transmit_chars()
295 		__ssp_transmit_char(ssp, ssp->port.x_char);  in __ssp_transmit_chars()
296 		ssp->port.icount.tx++;  in __ssp_transmit_chars()
297 		ssp->port.x_char = 0;  in __ssp_transmit_chars()
300 	if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) {  in __ssp_transmit_chars()
301 		sifive_serial_stop_tx(&ssp->port);  in __ssp_transmit_chars()
306 		__ssp_transmit_char(ssp, xmit->buf[xmit->tail]);  in __ssp_transmit_chars()
307 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);  in __ssp_transmit_chars()
308 		ssp->port.icount.tx++;  in __ssp_transmit_chars()
311 	} while (--count > 0);  in __ssp_transmit_chars()
314 		uart_write_wakeup(&ssp->port);  in __ssp_transmit_chars()
317 		sifive_serial_stop_tx(&ssp->port);  in __ssp_transmit_chars()
321  * __ssp_enable_txwm() - enable transmit watermark interrupts
325  * on the SiFive UART referred to by @ssp.
329 	if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)  in __ssp_enable_txwm()
332 	ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_enable_txwm()
333 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_txwm()
337  * __ssp_enable_rxwm() - enable receive watermark interrupts
341  * on the SiFive UART referred to by @ssp.
345 	if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)  in __ssp_enable_rxwm()
348 	ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_enable_rxwm()
349 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_rxwm()
353  * __ssp_disable_txwm() - disable transmit watermark interrupts
361 	if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))  in __ssp_disable_txwm()
364 	ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_disable_txwm()
365 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_txwm()
369  * __ssp_disable_rxwm() - disable receive watermark interrupts
377 	if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))  in __ssp_disable_rxwm()
380 	ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_disable_rxwm()
381 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_rxwm()
385  * __ssp_receive_char() - receive a byte from the UART
389  * Try to read a byte from the SiFive UART RX FIFO, referenced by
416  * __ssp_receive_chars() - receive multiple bytes from the UART
419  * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
422  * Context: Expects ssp->port.lock to be held by caller.
430 	for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {  in __ssp_receive_chars()
435 		ssp->port.icount.rx++;  in __ssp_receive_chars()
436 		uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);  in __ssp_receive_chars()
439 	tty_flip_buffer_push(&ssp->port.state->port);  in __ssp_receive_chars()
443  * __ssp_update_div() - calculate the divisor setting by the line rate
454 	div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;  in __ssp_update_div()
460  * __ssp_update_baud_rate() - set the UART "baud rate"
465  * SiFive UART described by @ssp and program it into the UART.  There may
472 	if (ssp->baud_rate == rate)  in __ssp_update_baud_rate()
475 	ssp->baud_rate = rate;  in __ssp_update_baud_rate()
480  * __ssp_set_stop_bits() - set the number of stop bits
484  * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
497 	v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;  in __ssp_set_stop_bits()
502  * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
545 	spin_lock(&ssp->port.lock);  in sifive_serial_irq()
549 		spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
558 	spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
601  * sifive_serial_clk_notifier() - clock post-rate-change notifier
607  * after a synchronous divide-by-two divider, so any CPU clock rate change
623 		 * left in the TX queue -- in other words, when the TX FIFO is  in sifive_serial_clk_notifier()
636 		udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));  in sifive_serial_clk_notifier()
639 	if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {  in sifive_serial_clk_notifier()
640 		ssp->port.uartclk = cnd->new_rate;  in sifive_serial_clk_notifier()
657 	if ((termios->c_cflag & CSIZE) != CS8) {  in sifive_serial_set_termios()
658 		dev_err_once(ssp->port.dev, "only 8-bit words supported\n");  in sifive_serial_set_termios()
659 		termios->c_cflag &= ~CSIZE;  in sifive_serial_set_termios()
660 		termios->c_cflag |= CS8;  in sifive_serial_set_termios()
662 	if (termios->c_iflag & (INPCK | PARMRK))  in sifive_serial_set_termios()
663 		dev_err_once(ssp->port.dev, "parity checking not supported\n");  in sifive_serial_set_termios()
664 	if (termios->c_iflag & BRKINT)  in sifive_serial_set_termios()
665 		dev_err_once(ssp->port.dev, "BREAK detection not supported\n");  in sifive_serial_set_termios()
666 	termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);  in sifive_serial_set_termios()
669 	nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;  in sifive_serial_set_termios()
674 				  ssp->port.uartclk / 16);  in sifive_serial_set_termios()
677 	spin_lock_irqsave(&ssp->port.lock, flags);  in sifive_serial_set_termios()
679 	/* Update the per-port timeout */  in sifive_serial_set_termios()
680 	uart_update_timeout(port, termios->c_cflag, rate);  in sifive_serial_set_termios()
682 	ssp->port.read_status_mask = 0;  in sifive_serial_set_termios()
687 	if ((termios->c_cflag & CREAD) == 0)  in sifive_serial_set_termios()
694 	spin_unlock_irqrestore(&ssp->port.lock, flags);  in sifive_serial_set_termios()
710 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_config_port()
716 	return -EINVAL;  in sifive_serial_verify_port()
721 	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;  in sifive_serial_type()
764 	struct earlycon_device *dev = con->data;  in early_sifive_serial_write()
765 	struct uart_port *port = &dev->port;  in early_sifive_serial_write()
773 	struct uart_port *port = &dev->port;  in early_sifive_serial_setup()
775 	if (!port->membase)  in early_sifive_serial_setup()
776 		return -ENODEV;  in early_sifive_serial_setup()
778 	dev->con->write = early_sifive_serial_write;  in early_sifive_serial_setup()
783 OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
784 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
807 	struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_write()
816 	if (ssp->port.sysrq)  in sifive_serial_console_write()
819 		locked = spin_trylock(&ssp->port.lock);  in sifive_serial_console_write()
821 		spin_lock(&ssp->port.lock);  in sifive_serial_console_write()
826 	uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);  in sifive_serial_console_write()
831 		spin_unlock(&ssp->port.lock);  in sifive_serial_console_write()
843 	if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)  in sifive_serial_console_setup()
844 		return -ENODEV;  in sifive_serial_console_setup()
846 	ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_setup()
848 		return -ENODEV;  in sifive_serial_console_setup()
853 	return uart_set_options(&ssp->port, co, baud, parity, bits, flow);  in sifive_serial_console_setup()
864 	.index		= -1,
878 	sifive_serial_console_ports[ssp->port.line] = ssp;  in __ssp_add_console_port()
883 	sifive_serial_console_ports[ssp->port.line] = NULL;  in __ssp_remove_console_port()
939 		return -EPROBE_DEFER;  in sifive_serial_probe()
942 	base = devm_ioremap_resource(&pdev->dev, mem);  in sifive_serial_probe()
944 		dev_err(&pdev->dev, "could not acquire device memory\n");  in sifive_serial_probe()
948 	clk = devm_clk_get_enabled(&pdev->dev, NULL);  in sifive_serial_probe()
950 		dev_err(&pdev->dev, "unable to find controller clock\n");  in sifive_serial_probe()
954 	id = of_alias_get_id(pdev->dev.of_node, "serial");  in sifive_serial_probe()
956 		dev_err(&pdev->dev, "missing aliases entry\n");  in sifive_serial_probe()
962 		dev_err(&pdev->dev, "too many UARTs (%d)\n", id);  in sifive_serial_probe()
963 		return -EINVAL;  in sifive_serial_probe()
967 	ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);  in sifive_serial_probe()
969 		return -ENOMEM;  in sifive_serial_probe()
971 	ssp->port.dev = &pdev->dev;  in sifive_serial_probe()
972 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_probe()
973 	ssp->port.iotype = UPIO_MEM;  in sifive_serial_probe()
974 	ssp->port.irq = irq;  in sifive_serial_probe()
975 	ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;  in sifive_serial_probe()
976 	ssp->port.ops = &sifive_serial_uops;  in sifive_serial_probe()
977 	ssp->port.line = id;  in sifive_serial_probe()
978 	ssp->port.mapbase = mem->start;  in sifive_serial_probe()
979 	ssp->port.membase = base;  in sifive_serial_probe()
980 	ssp->dev = &pdev->dev;  in sifive_serial_probe()
981 	ssp->clk = clk;  in sifive_serial_probe()
982 	ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;  in sifive_serial_probe()
984 	r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
986 		dev_err(&pdev->dev, "could not register clock notifier: %d\n",  in sifive_serial_probe()
992 	ssp->port.uartclk = clk_get_rate(ssp->clk);  in sifive_serial_probe()
993 	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;  in sifive_serial_probe()
1008 	r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,  in sifive_serial_probe()
1009 			dev_name(&pdev->dev), ssp);  in sifive_serial_probe()
1011 		dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);  in sifive_serial_probe()
1017 	r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_probe()
1019 		dev_err(&pdev->dev, "could not add uart: %d\n", r);  in sifive_serial_probe()
1027 	free_irq(ssp->port.irq, ssp);  in sifive_serial_probe()
1029 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
1039 	uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_remove()
1040 	free_irq(ssp->port.irq, ssp);  in sifive_serial_remove()
1041 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_remove()
1047 	{ .compatible = "sifive,fu540-c000-uart0" },
1048 	{ .compatible = "sifive,uart0" },
1091 MODULE_DESCRIPTION("SiFive UART serial driver");