Lines Matching +full:odd +full:- +full:parity
1 /* SPDX-License-Identifier: GPL-2.0 */
42 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
43 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
44 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
45 #define SCSMR_PE BIT(5) /* Parity Enable */
46 #define SCSMR_ODD BIT(4) /* Odd Parity */
66 /* Serial Control Register, HSCIF-only bits */
74 #define SCI_PER BIT(3) /* Parity Error */
91 #define SCIF_PER BIT(2) /* Parity Error */
95 #define SCIF_PERC 0xf000 /* Number of Parity Errors */
161 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
162 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
163 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
168 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
171 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
173 (to_sci_port(port)->params->error_clear)
175 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
177 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)