Lines Matching refs:membase
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
230 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
232 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
239 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
241 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
243 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
245 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
254 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
259 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
272 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
286 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
288 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
330 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
343 writel(port->x_char, port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
355 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
362 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_chars()
377 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
392 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
404 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
419 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
423 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
425 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
427 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
429 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
431 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
474 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
549 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
552 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
555 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
560 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
642 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
647 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
655 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
663 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
696 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
702 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
705 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
724 if (!device->port.membase) in mvebu_uart_early_console_setup()
740 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
748 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
755 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
771 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
772 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
774 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
775 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
782 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
785 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
786 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
806 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
859 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
860 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
861 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
862 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
863 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
865 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
867 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
880 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
881 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
882 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
883 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
884 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
886 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
888 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
956 port->membase = devm_ioremap_resource(&pdev->dev, reg); in mvebu_uart_probe()
957 if (IS_ERR(port->membase)) in mvebu_uart_probe()
958 return PTR_ERR(port->membase); in mvebu_uart_probe()
1015 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
1017 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()