Lines Matching refs:UART_INTR
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) macro
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
230 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
232 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
243 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
245 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
429 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
431 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
474 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
772 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
775 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
785 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
786 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
862 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
883 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()