Lines Matching +full:tbg +full:- +full:a +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Armada-3700 Serial Driver
11 #include <linux/clk-provider.h>
77 * error in Marvell's documentation. Hence following CLK_DIS macros are swapped.
106 #define MVEBU_UART_TYPE "mvebu-uart"
134 /* Driver data, a structure for each UART port */
165 return (struct mvebu_uart *)port->private_data; in to_mvuart()
168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
190 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_tx_empty()
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
192 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
222 struct circ_buf *xmit = &port->state->xmit; in mvebu_uart_start_tx()
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
226 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in mvebu_uart_start_tx()
227 port->icount.tx++; in mvebu_uart_start_tx()
230 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
232 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
239 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
241 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
243 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
245 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
253 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_break_ctl()
254 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
255 if (brk == -1) in mvebu_uart_break_ctl()
259 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
260 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_break_ctl()
265 struct tty_port *tport = &port->state->port; in mvebu_uart_rx_chars()
272 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
275 port->icount.rx++; in mvebu_uart_rx_chars()
278 port->icount.parity++; in mvebu_uart_rx_chars()
286 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
288 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
292 port->icount.brk++; in mvebu_uart_rx_chars()
299 port->icount.overrun++; in mvebu_uart_rx_chars()
302 port->icount.frame++; in mvebu_uart_rx_chars()
307 if (status & port->ignore_status_mask & STAT_PAR_ERR) in mvebu_uart_rx_chars()
310 status &= port->read_status_mask; in mvebu_uart_rx_chars()
315 status &= ~port->ignore_status_mask; in mvebu_uart_rx_chars()
330 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
338 struct circ_buf *xmit = &port->state->xmit; in mvebu_uart_tx_chars()
342 if (port->x_char) { in mvebu_uart_tx_chars()
343 writel(port->x_char, port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
344 port->icount.tx++; in mvebu_uart_tx_chars()
345 port->x_char = 0; in mvebu_uart_tx_chars()
354 for (count = 0; count < port->fifosize; count++) { in mvebu_uart_tx_chars()
355 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in mvebu_uart_tx_chars()
357 port->icount.tx++; in mvebu_uart_tx_chars()
362 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_chars()
377 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
392 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
404 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
419 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
423 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
425 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
427 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
429 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
431 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
433 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_startup()
435 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], in mvebu_uart_startup()
436 mvebu_uart_isr, port->irqflags, in mvebu_uart_startup()
437 dev_name(port->dev), port); in mvebu_uart_startup()
439 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
440 mvuart->irq[UART_IRQ_SUM]); in mvebu_uart_startup()
445 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
446 mvebu_uart_rx_isr, port->irqflags, in mvebu_uart_startup()
447 dev_name(port->dev), port); in mvebu_uart_startup()
449 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
450 mvuart->irq[UART_RX_IRQ]); in mvebu_uart_startup()
454 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], in mvebu_uart_startup()
455 mvebu_uart_tx_isr, port->irqflags, in mvebu_uart_startup()
456 dev_name(port->dev), in mvebu_uart_startup()
459 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
460 mvuart->irq[UART_TX_IRQ]); in mvebu_uart_startup()
461 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
474 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
476 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_shutdown()
477 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); in mvebu_uart_shutdown()
479 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); in mvebu_uart_shutdown()
480 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); in mvebu_uart_shutdown()
490 if (!port->uartclk) in mvebu_uart_baud_rate_set()
495 * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 in mvebu_uart_baud_rate_set()
497 * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) in mvebu_uart_baud_rate_set()
503 * baudrate = tbg / (d1 * d2 * d * 16) in mvebu_uart_baud_rate_set()
507 * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) in mvebu_uart_baud_rate_set()
525 * Member port->uartclk is either xtal clock rate or TBG clock rate in mvebu_uart_baud_rate_set()
532 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
540 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
549 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
552 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
555 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
560 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
562 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); in mvebu_uart_baud_rate_set()
572 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_set_termios()
574 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | in mvebu_uart_set_termios()
577 if (termios->c_iflag & INPCK) in mvebu_uart_set_termios()
578 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; in mvebu_uart_set_termios()
580 port->ignore_status_mask = 0; in mvebu_uart_set_termios()
581 if (termios->c_iflag & IGNPAR) in mvebu_uart_set_termios()
582 port->ignore_status_mask |= in mvebu_uart_set_termios()
585 if ((termios->c_cflag & CREAD) == 0) in mvebu_uart_set_termios()
586 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; in mvebu_uart_set_termios()
592 * rate. If port->uartclk is not available, then in mvebu_uart_set_termios()
596 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * in mvebu_uart_set_termios()
598 max_baud = port->uartclk / 80; in mvebu_uart_set_termios()
609 termios->c_iflag &= INPCK | IGNPAR; in mvebu_uart_set_termios()
610 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); in mvebu_uart_set_termios()
611 termios->c_cflag &= CREAD | CBAUD; in mvebu_uart_set_termios()
612 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); in mvebu_uart_set_termios()
613 termios->c_cflag |= CS8; in mvebu_uart_set_termios()
618 uart_update_timeout(port, termios->c_cflag, baud); in mvebu_uart_set_termios()
621 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_set_termios()
642 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
647 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
655 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
663 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
696 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
702 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
705 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
712 const char *s, in mvebu_uart_putc_early_write() argument
715 struct earlycon_device *dev = con->data; in mvebu_uart_putc_early_write()
717 uart_console_write(&dev->port, s, n, mvebu_uart_putc); in mvebu_uart_putc_early_write()
724 if (!device->port.membase) in mvebu_uart_early_console_setup()
725 return -ENODEV; in mvebu_uart_early_console_setup()
727 device->con->write = mvebu_uart_putc_early_write; in mvebu_uart_early_console_setup()
733 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
740 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
748 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
755 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
758 static void mvebu_uart_console_write(struct console *co, const char *s, in mvebu_uart_console_write() argument
761 struct uart_port *port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_write()
767 locked = spin_trylock_irqsave(&port->lock, flags); in mvebu_uart_console_write()
769 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_console_write()
771 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
772 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
774 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
775 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
777 uart_console_write(port, s, count, mvebu_uart_console_putchar); in mvebu_uart_console_write()
782 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
785 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
786 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
790 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_console_write()
801 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) in mvebu_uart_console_setup()
802 return -EINVAL; in mvebu_uart_console_setup()
804 port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_setup()
806 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
807 pr_debug("console on ttyMV%i not present\n", co->index); in mvebu_uart_console_setup()
808 return -ENODEV; in mvebu_uart_console_setup()
825 .index = -1,
854 struct uart_port *port = mvuart->port; in mvebu_uart_suspend()
859 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
860 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
861 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
862 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
863 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
865 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
867 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
877 struct uart_port *port = mvuart->port; in mvebu_uart_resume()
880 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
881 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
882 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
883 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
884 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
886 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
888 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
910 &pdev->dev); in mvebu_uart_probe()
916 dev_err(&pdev->dev, "no registers defined\n"); in mvebu_uart_probe()
917 return -EINVAL; in mvebu_uart_probe()
920 /* Assume that all UART ports have a DT alias or none has */ in mvebu_uart_probe()
921 id = of_alias_get_id(pdev->dev.of_node, "serial"); in mvebu_uart_probe()
922 if (!pdev->dev.of_node || id < 0) in mvebu_uart_probe()
923 pdev->id = uart_num_counter++; in mvebu_uart_probe()
925 pdev->id = id; in mvebu_uart_probe()
927 if (pdev->id >= MVEBU_NR_UARTS) { in mvebu_uart_probe()
928 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", in mvebu_uart_probe()
930 return -EINVAL; in mvebu_uart_probe()
933 port = &mvebu_uart_ports[pdev->id]; in mvebu_uart_probe()
935 spin_lock_init(&port->lock); in mvebu_uart_probe()
937 port->dev = &pdev->dev; in mvebu_uart_probe()
938 port->type = PORT_MVEBU; in mvebu_uart_probe()
939 port->ops = &mvebu_uart_ops; in mvebu_uart_probe()
940 port->regshift = 0; in mvebu_uart_probe()
942 port->fifosize = 32; in mvebu_uart_probe()
943 port->iotype = UPIO_MEM32; in mvebu_uart_probe()
944 port->flags = UPF_FIXED_PORT; in mvebu_uart_probe()
945 port->line = pdev->id; in mvebu_uart_probe()
950 * array so called ->irq[]. in mvebu_uart_probe()
952 port->irq = 0; in mvebu_uart_probe()
953 port->irqflags = 0; in mvebu_uart_probe()
954 port->mapbase = reg->start; in mvebu_uart_probe()
956 port->membase = devm_ioremap_resource(&pdev->dev, reg); in mvebu_uart_probe()
957 if (IS_ERR(port->membase)) in mvebu_uart_probe()
958 return PTR_ERR(port->membase); in mvebu_uart_probe()
960 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), in mvebu_uart_probe()
963 return -ENOMEM; in mvebu_uart_probe()
966 mvuart->data = (struct mvebu_uart_driver_data *)match->data; in mvebu_uart_probe()
967 mvuart->port = port; in mvebu_uart_probe()
969 port->private_data = mvuart; in mvebu_uart_probe()
973 mvuart->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_uart_probe()
974 if (IS_ERR(mvuart->clk)) { in mvebu_uart_probe()
975 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) in mvebu_uart_probe()
976 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
979 dev_err(&pdev->dev, "unable to get UART clock\n"); in mvebu_uart_probe()
980 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
983 if (!clk_prepare_enable(mvuart->clk)) in mvebu_uart_probe()
984 port->uartclk = clk_get_rate(mvuart->clk); in mvebu_uart_probe()
994 mvuart->irq[UART_IRQ_SUM] = irq; in mvebu_uart_probe()
998 * only make use of uart-rx and uart-tx interrupts, do not use in mvebu_uart_probe()
999 * uart-sum of UART0 port. in mvebu_uart_probe()
1001 irq = platform_get_irq_byname(pdev, "uart-rx"); in mvebu_uart_probe()
1005 mvuart->irq[UART_RX_IRQ] = irq; in mvebu_uart_probe()
1007 irq = platform_get_irq_byname(pdev, "uart-tx"); in mvebu_uart_probe()
1011 mvuart->irq[UART_TX_IRQ] = irq; in mvebu_uart_probe()
1015 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
1017 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
1049 .compatible = "marvell,armada-3700-uart",
1053 .compatible = "marvell,armada-3700-uart-ext",
1062 .name = "mvebu-uart",
1071 /* This code is based on clk-fixed-factor.c driver and modified. */
1094 struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx])
1114 * otherwise kernel's boot log stops working - we need to ensure that in mvebu_uart_clock_prepare()
1115 * UART baudrate does not change during this setup. It is a one time in mvebu_uart_clock_prepare()
1120 * UART_BRDV (reg1) needs to be protected by a lock. in mvebu_uart_clock_prepare()
1125 if (uart_clock_base->configured) { in mvebu_uart_clock_prepare()
1130 parent_clock_idx = uart_clock_base->parent_idx; in mvebu_uart_clock_prepare()
1131 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; in mvebu_uart_clock_prepare()
1133 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1135 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { in mvebu_uart_clock_prepare()
1137 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()
1139 d1 = uart_clock_base->div; in mvebu_uart_clock_prepare()
1152 /* Note that uart_clock_base->parent_rates[i] may not be available */ in mvebu_uart_clock_prepare()
1153 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; in mvebu_uart_clock_prepare()
1168 /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ in mvebu_uart_clock_prepare()
1177 /* Use XTAL, TBG bits are then ignored */ in mvebu_uart_clock_prepare()
1181 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1185 val = readl(uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1194 writel(val, uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1197 uart_clock_base->configured = true; in mvebu_uart_clock_prepare()
1214 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_enable()
1216 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_enable()
1221 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_enable()
1238 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_disable()
1240 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_disable()
1245 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_disable()
1257 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_is_enabled()
1259 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_is_enabled()
1273 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); in mvebu_uart_clock_save_context()
1274 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); in mvebu_uart_clock_save_context()
1288 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); in mvebu_uart_clock_restore_context()
1289 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); in mvebu_uart_clock_restore_context()
1300 return parent_rate / uart_clock_base->div; in mvebu_uart_clock_recalc_rate()
1310 return *parent_rate / uart_clock_base->div; in mvebu_uart_clock_round_rate()
1318 * mvebu_uart_clock_round_rate returns values that ensure this call is a in mvebu_uart_clock_set_rate()
1344 uart_clock->clk_hw.init = &init; in mvebu_uart_clock_register()
1352 return devm_clk_hw_register(dev, &uart_clock->clk_hw); in mvebu_uart_clock_register()
1358 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", in mvebu_uart_clock_probe()
1359 "TBG-A-S", "TBG-B-S", in mvebu_uart_clock_probe()
1364 struct device *dev = &pdev->dev; in mvebu_uart_clock_probe()
1371 ARRAY_SIZE(uart_clock_base->clocks)); in mvebu_uart_clock_probe()
1373 ARRAY_SIZE(uart_clock_base->parent_rates)); in mvebu_uart_clock_probe()
1379 return -ENOMEM; in mvebu_uart_clock_probe()
1384 return -ENOENT; in mvebu_uart_clock_probe()
1393 * by a lock shared between clock and UART driver. in mvebu_uart_clock_probe()
1395 uart_clock_base->reg1 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1397 if (!uart_clock_base->reg1) in mvebu_uart_clock_probe()
1398 return -ENOMEM; in mvebu_uart_clock_probe()
1403 return -ENOENT; in mvebu_uart_clock_probe()
1411 * conflicts with UART2 driver. Access to UART_BRDV is protected by a in mvebu_uart_clock_probe()
1414 uart_clock_base->reg2 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1416 if (!uart_clock_base->reg2) in mvebu_uart_clock_probe()
1417 return -ENOMEM; in mvebu_uart_clock_probe()
1424 return -ENOMEM; in mvebu_uart_clock_probe()
1426 hw_clk_data->num = ARRAY_SIZE(uart_clk_names); in mvebu_uart_clock_probe()
1428 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; in mvebu_uart_clock_probe()
1429 uart_clock_base->clocks[i].clock_idx = i; in mvebu_uart_clock_probe()
1432 parent_clk_idx = -1; in mvebu_uart_clock_probe()
1437 if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) in mvebu_uart_clock_probe()
1438 return -EPROBE_DEFER; in mvebu_uart_clock_probe()
1439 dev_warn(dev, "Couldn't get the parent clock %s: %ld\n", in mvebu_uart_clock_probe()
1446 dev_warn(dev, "Couldn't enable parent clock %s: %d\n", in mvebu_uart_clock_probe()
1451 uart_clock_base->parent_rates[i] = rate; in mvebu_uart_clock_probe()
1455 * Calculate the smallest TBG d1 and d2 divisors that in mvebu_uart_clock_probe()
1473 * When UART clock uses XTAL clock as a source then it in mvebu_uart_clock_probe()
1484 * Choose TBG clock source with the smallest divisors. Use XTAL in mvebu_uart_clock_probe()
1485 * clock source only in case TBG is not available as XTAL cannot in mvebu_uart_clock_probe()
1488 if (parent_clk_idx == -1 || in mvebu_uart_clock_probe()
1502 if (parent_clk_idx == -1) { in mvebu_uart_clock_probe()
1504 return -ENOENT; in mvebu_uart_clock_probe()
1507 uart_clock_base->parent_idx = parent_clk_idx; in mvebu_uart_clock_probe()
1508 uart_clock_base->div = div; in mvebu_uart_clock_probe()
1510 dev_notice(dev, "Using parent clock %s as base UART clock\n", in mvebu_uart_clock_probe()
1515 &uart_clock_base->clocks[i], in mvebu_uart_clock_probe()
1530 { .compatible = "marvell,armada-3700-uart-clock", },
1537 .name = "mvebu-uart-clock",