Lines Matching full:tbg
495 * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 in mvebu_uart_baud_rate_set()
503 * baudrate = tbg / (d1 * d2 * d * 16) in mvebu_uart_baud_rate_set()
507 * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) in mvebu_uart_baud_rate_set()
525 * Member port->uartclk is either xtal clock rate or TBG clock rate in mvebu_uart_baud_rate_set()
1168 /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ in mvebu_uart_clock_prepare()
1177 /* Use XTAL, TBG bits are then ignored */ in mvebu_uart_clock_prepare()
1358 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", in mvebu_uart_clock_probe()
1359 "TBG-A-S", "TBG-B-S", in mvebu_uart_clock_probe()
1455 * Calculate the smallest TBG d1 and d2 divisors that in mvebu_uart_clock_probe()
1484 * Choose TBG clock source with the smallest divisors. Use XTAL in mvebu_uart_clock_probe()
1485 * clock source only in case TBG is not available as XTAL cannot in mvebu_uart_clock_probe()