60 #define MSM_UART_CR				0x0010  macro
405 	msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);  in msm_wait_for_xmitr()
462 		msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);  in msm_complete_tx_dma()
463 		msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);  in msm_complete_tx_dma()
568 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_complete_rx_dma()
659 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_start_rx_dma()
660 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
682 	msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);  in msm_start_rx_dma()
683 	msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
685 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_start_rx_dma()
687 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
725 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_handle_rx_dm()
780 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_handle_rx_dm()
782 	msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_handle_rx_dm()
801 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_handle_rx()
945 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);  in msm_handle_delta_cts()
965 		msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);  in msm_uart_irq()
971 			msm_write(port, val, MSM_UART_CR);  in msm_uart_irq()
973 			msm_write(port, val, MSM_UART_CR);  in msm_uart_irq()
1012 	msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);  in msm_reset()
1013 	msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);  in msm_reset()
1014 	msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_reset()
1015 	msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);  in msm_reset()
1016 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);  in msm_reset()
1017 	msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);  in msm_reset()
1036 		msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);  in msm_set_mctrl()
1046 		msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);  in msm_break_ctl()
1048 		msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);  in msm_break_ctl()
1168 	msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);  in msm_set_baud_rate()
1172 	msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);  in msm_set_baud_rate()
1181 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_set_baud_rate()
1183 		msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_set_baud_rate()
1470 			msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);  in msm_poll_get_char_dm()
1474 			msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_poll_get_char_dm()
1476 			msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_poll_get_char_dm()