Lines Matching +full:gpio +full:- +full:wo +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
16 #include <linux/gpio/driver.h>
61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
139 * 00 -> 5 bit words
140 * 01 -> 6 bit words
141 * 10 -> 7 bit words
142 * 11 -> 8 bit words
147 * 0 -> 1 stop bit
148 * 1 -> 1-1.5 stop bits if
154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
186 * 00 -> no transmitter flow
188 * 01 -> receiver compares
192 * 10 -> receiver compares
196 * 11 -> receiver compares
205 * 00 -> no received flow
207 * 01 -> transmitter generates
209 * 10 -> transmitter generates
211 * 11 -> transmitter generates
286 struct gpio_chip gpio; member
307 regmap_read(one->regmap, reg, &val); in max310x_port_read()
316 regmap_write(one->regmap, reg, val); in max310x_port_write()
323 regmap_update_bits(one->regmap, reg, mask, val); in max310x_port_update()
332 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); in max3107_detect()
338 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3107_detect()
339 return -ENODEV; in max3107_detect()
354 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); in max3108_detect()
359 dev_err(dev, "%s not present\n", s->devtype->name); in max3108_detect()
360 return -ENODEV; in max3108_detect()
372 ret = s->if_cfg->extended_reg_enable(dev, true); in max3109_detect()
376 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); in max3109_detect()
377 s->if_cfg->extended_reg_enable(dev, false); in max3109_detect()
380 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3109_detect()
381 return -ENODEV; in max3109_detect()
402 ret = s->if_cfg->extended_reg_enable(dev, true); in max14830_detect()
406 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); in max14830_detect()
407 s->if_cfg->extended_reg_enable(dev, false); in max14830_detect()
410 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max14830_detect()
411 return -ENODEV; in max14830_detect()
534 * in case if the requested baud is too high for the pre-defined in max310x_set_baud()
537 div = port->uartclk / baud; in max310x_set_baud()
556 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
565 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
585 long besterr = -1; in max310x_set_ref_clk()
631 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); in max310x_set_ref_clk()
635 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
641 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); in max310x_set_ref_clk()
654 regmap_raw_write(one->regmap, MAX310X_THR_REG, txbuf, len); in max310x_batch_write()
661 regmap_raw_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); in max310x_batch_read()
669 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { in max310x_handle_rx()
671 * Break condition, parity checking, framing errors -- they in max310x_handle_rx()
672 * are all ignored. That means that we can do a batch-read. in max310x_handle_rx()
682 max310x_batch_read(port, one->rx_buf, rxlen); in max310x_handle_rx()
684 port->icount.rx += rxlen; in max310x_handle_rx()
686 sts &= port->read_status_mask; in max310x_handle_rx()
689 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); in max310x_handle_rx()
690 port->icount.overrun++; in max310x_handle_rx()
693 for (i = 0; i < (rxlen - 1); ++i) in max310x_handle_rx()
694 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); in max310x_handle_rx()
702 one->rx_buf[rxlen-1], flag); in max310x_handle_rx()
705 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
706 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); in max310x_handle_rx()
707 port->icount.buf_overrun++; in max310x_handle_rx()
709 rxlen = port->fifosize; in max310x_handle_rx()
712 while (rxlen--) { in max310x_handle_rx()
719 port->icount.rx++; in max310x_handle_rx()
724 port->icount.brk++; in max310x_handle_rx()
728 port->icount.parity++; in max310x_handle_rx()
730 port->icount.frame++; in max310x_handle_rx()
732 port->icount.overrun++; in max310x_handle_rx()
734 sts &= port->read_status_mask; in max310x_handle_rx()
748 if (sts & port->ignore_status_mask) in max310x_handle_rx()
755 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
760 struct circ_buf *xmit = &port->state->xmit; in max310x_handle_tx()
763 if (unlikely(port->x_char)) { in max310x_handle_tx()
764 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
765 port->icount.tx++; in max310x_handle_tx()
766 port->x_char = 0; in max310x_handle_tx()
775 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in max310x_handle_tx()
779 txlen = port->fifosize - txlen; in max310x_handle_tx()
783 /* It's a circ buffer -- wrap around. in max310x_handle_tx()
785 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); in max310x_handle_tx()
786 max310x_batch_write(port, xmit->buf, to_send - until_end); in max310x_handle_tx()
788 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); in max310x_handle_tx()
792 port->icount.tx += to_send; in max310x_handle_tx()
793 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); in max310x_handle_tx()
804 schedule_work(&one->tx_work); in max310x_start_tx()
809 struct uart_port *port = &s->p[portno].port; in max310x_port_irq()
841 if (s->devtype->nr > 1) { in max310x_ist()
845 WARN_ON_ONCE(regmap_read(s->regmap, in max310x_ist()
847 val = ((1 << s->devtype->nr) - 1) & ~val; in max310x_ist()
850 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) in max310x_ist()
865 max310x_handle_tx(&one->port); in max310x_tx_proc()
887 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
889 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
897 schedule_work(&one->md_work); in max310x_set_mctrl()
915 termios->c_cflag &= ~CMSPAR; in max310x_set_termios()
918 switch (termios->c_cflag & CSIZE) { in max310x_set_termios()
934 if (termios->c_cflag & PARENB) { in max310x_set_termios()
936 if (!(termios->c_cflag & PARODD)) in max310x_set_termios()
941 if (termios->c_cflag & CSTOPB) in max310x_set_termios()
948 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
949 if (termios->c_iflag & INPCK) in max310x_set_termios()
950 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
952 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in max310x_set_termios()
953 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
956 port->ignore_status_mask = 0; in max310x_set_termios()
957 if (termios->c_iflag & IGNBRK) in max310x_set_termios()
958 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
959 if (!(termios->c_cflag & CREAD)) in max310x_set_termios()
960 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
966 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
967 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
972 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { in max310x_set_termios()
978 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in max310x_set_termios()
980 if (termios->c_cflag & CRTSCTS) { in max310x_set_termios()
982 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in max310x_set_termios()
986 if (termios->c_iflag & IXON) in max310x_set_termios()
989 if (termios->c_iflag & IXOFF) { in max310x_set_termios()
990 port->status |= UPSTAT_AUTOXOFF; in max310x_set_termios()
999 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { in max310x_set_termios()
1007 port->uartclk / 16 / 0xffff, in max310x_set_termios()
1008 port->uartclk / 4); in max310x_set_termios()
1014 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
1022 delay = (one->port.rs485.delay_rts_before_send << 4) | in max310x_rs_proc()
1023 one->port.rs485.delay_rts_after_send; in max310x_rs_proc()
1024 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); in max310x_rs_proc()
1026 if (one->port.rs485.flags & SER_RS485_ENABLED) { in max310x_rs_proc()
1029 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_rs_proc()
1033 max310x_port_update(&one->port, MAX310X_MODE1_REG, in max310x_rs_proc()
1035 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_rs_proc()
1044 if ((rs485->delay_rts_before_send > 0x0f) || in max310x_rs485_config()
1045 (rs485->delay_rts_after_send > 0x0f)) in max310x_rs485_config()
1046 return -ERANGE; in max310x_rs485_config()
1048 port->rs485 = *rs485; in max310x_rs485_config()
1050 schedule_work(&one->rs_work); in max310x_rs485_config()
1057 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_startup()
1060 s->devtype->power(port, 1); in max310x_startup()
1073 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | in max310x_startup()
1074 clamp(port->rs485.delay_rts_after_send, 0U, 15U); in max310x_startup()
1077 if (port->rs485.flags & SER_RS485_ENABLED) { in max310x_startup()
1082 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_startup()
1105 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_shutdown()
1110 s->devtype->power(port, 0); in max310x_shutdown()
1115 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
1117 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
1129 port->type = PORT_MAX310X; in max310x_config_port()
1134 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) in max310x_verify_port()
1135 return -EINVAL; in max310x_verify_port()
1136 if (s->irq != port->irq) in max310x_verify_port()
1137 return -EINVAL; in max310x_verify_port()
1170 for (i = 0; i < s->devtype->nr; i++) { in max310x_suspend()
1171 uart_suspend_port(&max310x_uart, &s->p[i].port); in max310x_suspend()
1172 s->devtype->power(&s->p[i].port, 0); in max310x_suspend()
1183 for (i = 0; i < s->devtype->nr; i++) { in max310x_resume()
1184 s->devtype->power(&s->p[i].port, 1); in max310x_resume()
1185 uart_resume_port(&max310x_uart, &s->p[i].port); in max310x_resume()
1198 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get()
1208 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set()
1217 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input()
1228 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output()
1242 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set_config()
1255 return -ENOTSUPP; in max310x_gpio_set_config()
1275 for (i = 0; i < devtype->nr; i++) in max310x_probe()
1280 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); in max310x_probe()
1283 return -ENOMEM; in max310x_probe()
1287 device_property_read_u32(dev, "clock-frequency", &uartclk); in max310x_probe()
1289 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; in max310x_probe()
1291 s->clk = devm_clk_get_optional(dev, "xtal"); in max310x_probe()
1293 s->clk = devm_clk_get_optional(dev, "osc"); in max310x_probe()
1294 if (IS_ERR(s->clk)) in max310x_probe()
1295 return PTR_ERR(s->clk); in max310x_probe()
1297 ret = clk_prepare_enable(s->clk); in max310x_probe()
1301 freq = clk_get_rate(s->clk); in max310x_probe()
1306 ret = -EINVAL; in max310x_probe()
1320 ret = -ERANGE; in max310x_probe()
1324 s->regmap = regmaps[0]; in max310x_probe()
1325 s->devtype = devtype; in max310x_probe()
1326 s->if_cfg = if_cfg; in max310x_probe()
1330 ret = devtype->detect(dev); in max310x_probe()
1334 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1346 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); in max310x_probe()
1352 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1357 ret = -ERANGE; in max310x_probe()
1362 s->p[i].port.line = line; in max310x_probe()
1363 s->p[i].port.dev = dev; in max310x_probe()
1364 s->p[i].port.irq = irq; in max310x_probe()
1365 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1366 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1367 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1368 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1369 s->p[i].port.iobase = i; in max310x_probe()
1370 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1371 s->p[i].port.uartclk = uartclk; in max310x_probe()
1372 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1373 s->p[i].port.rs485_supported = max310x_rs485_supported; in max310x_probe()
1374 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1375 s->p[i].regmap = regmaps[i]; in max310x_probe()
1378 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1380 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1382 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); in max310x_probe()
1384 INIT_WORK(&s->p[i].md_work, max310x_md_proc); in max310x_probe()
1386 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); in max310x_probe()
1389 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1391 s->p[i].port.dev = NULL; in max310x_probe()
1397 devtype->power(&s->p[i].port, 0); in max310x_probe()
1401 /* Setup GPIO cotroller */ in max310x_probe()
1402 s->gpio.owner = THIS_MODULE; in max310x_probe()
1403 s->gpio.parent = dev; in max310x_probe()
1404 s->gpio.label = devtype->name; in max310x_probe()
1405 s->gpio.direction_input = max310x_gpio_direction_input; in max310x_probe()
1406 s->gpio.get = max310x_gpio_get; in max310x_probe()
1407 s->gpio.direction_output= max310x_gpio_direction_output; in max310x_probe()
1408 s->gpio.set = max310x_gpio_set; in max310x_probe()
1409 s->gpio.set_config = max310x_gpio_set_config; in max310x_probe()
1410 s->gpio.base = -1; in max310x_probe()
1411 s->gpio.ngpio = devtype->nr * 4; in max310x_probe()
1412 s->gpio.can_sleep = 1; in max310x_probe()
1413 ret = devm_gpiochip_add_data(dev, &s->gpio, s); in max310x_probe()
1427 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1428 if (s->p[i].port.dev) { in max310x_probe()
1429 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1430 clear_bit(s->p[i].port.line, max310x_lines); in max310x_probe()
1435 clk_disable_unprepare(s->clk); in max310x_probe()
1445 for (i = 0; i < s->devtype->nr; i++) { in max310x_remove()
1446 cancel_work_sync(&s->p[i].tx_work); in max310x_remove()
1447 cancel_work_sync(&s->p[i].md_work); in max310x_remove()
1448 cancel_work_sync(&s->p[i].rs_work); in max310x_remove()
1449 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_remove()
1450 clear_bit(s->p[i].port.line, max310x_lines); in max310x_remove()
1451 s->devtype->power(&s->p[i].port, 0); in max310x_remove()
1454 clk_disable_unprepare(s->clk); in max310x_remove()
1482 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max310x_spi_extended_reg_enable()
1499 spi->bits_per_word = 8; in max310x_spi_probe()
1500 spi->mode = spi->mode ? : SPI_MODE_0; in max310x_spi_probe()
1501 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; in max310x_spi_probe()
1506 devtype = device_get_match_data(&spi->dev); in max310x_spi_probe()
1508 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; in max310x_spi_probe()
1510 for (i = 0; i < devtype->nr; i++) { in max310x_spi_probe()
1517 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); in max310x_spi_probe()
1522 max310x_remove(&spi->dev); in max310x_spi_remove()
1575 * UART1 - UART0 = 0x10 in max310x_i2c_slave_addr()
1576 * UART2 - UART1 = 0x20 + 0x10 in max310x_i2c_slave_addr()
1577 * UART3 - UART2 = 0x10 in max310x_i2c_slave_addr()
1580 addr -= nr * 0x10; in max310x_i2c_slave_addr()
1583 addr -= 0x20; in max310x_i2c_slave_addr()
1591 device_get_match_data(&client->dev); in max310x_i2c_probe()
1597 if (client->addr < devtype->slave_addr.min || in max310x_i2c_probe()
1598 client->addr > devtype->slave_addr.max) in max310x_i2c_probe()
1599 return dev_err_probe(&client->dev, -EINVAL, in max310x_i2c_probe()
1601 client->addr, devtype->slave_addr.min, in max310x_i2c_probe()
1602 devtype->slave_addr.max); in max310x_i2c_probe()
1606 for (i = 1; i < devtype->nr; i++) { in max310x_i2c_probe()
1607 port_addr = max310x_i2c_slave_addr(client->addr, i); in max310x_i2c_probe()
1608 port_client = devm_i2c_new_dummy_device(&client->dev, in max310x_i2c_probe()
1609 client->adapter, in max310x_i2c_probe()
1615 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, in max310x_i2c_probe()
1616 regmaps, client->irq); in max310x_i2c_probe()
1621 max310x_remove(&client->dev); in max310x_i2c_remove()