Lines Matching +full:neo +full:- +full:8
1 // SPDX-License-Identifier: GPL-2.0+
20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
28 * value of the Neo card.
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
56 /* Turn on table D, with 8 char hi/low watermarks */ in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
60 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_cts_flow_control()
61 ch->ch_t_tlevel = 8; in neo_set_cts_flow_control()
63 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
69 ier = readb(&ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
70 efr = readb(&ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); in neo_set_rts_flow_control()
83 writeb(0, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
86 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_rts_flow_control()
89 ch->ch_r_watermark = 4; in neo_set_rts_flow_control()
91 writeb(56, &ch->ch_neo_uart->rfifo); in neo_set_rts_flow_control()
92 ch->ch_r_tlevel = 56; in neo_set_rts_flow_control()
94 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
97 * From the Neo UART spec sheet: in neo_set_rts_flow_control()
99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after in neo_set_rts_flow_control()
102 ch->ch_mostat |= (UART_MCR_RTS); in neo_set_rts_flow_control()
109 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
110 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); in neo_set_ixon_flow_control()
122 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
125 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixon_flow_control()
128 ch->ch_r_watermark = 4; in neo_set_ixon_flow_control()
130 writeb(32, &ch->ch_neo_uart->rfifo); in neo_set_ixon_flow_control()
131 ch->ch_r_tlevel = 32; in neo_set_ixon_flow_control()
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixon_flow_control()
135 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixon_flow_control()
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixon_flow_control()
138 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixon_flow_control()
140 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
146 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
147 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); in neo_set_ixoff_flow_control()
160 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
163 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
165 /* Turn on table D, with 8 char hi/low watermarks */ in neo_set_ixoff_flow_control()
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixoff_flow_control()
168 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_ixoff_flow_control()
169 ch->ch_t_tlevel = 8; in neo_set_ixoff_flow_control()
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixoff_flow_control()
173 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixoff_flow_control()
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixoff_flow_control()
176 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixoff_flow_control()
178 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
184 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
185 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); in neo_set_no_input_flow_control()
195 if (ch->ch_c_iflag & IXON) in neo_set_no_input_flow_control()
201 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
204 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
206 /* Turn on table D, with 8 char hi/low watermarks */ in neo_set_no_input_flow_control()
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_input_flow_control()
209 ch->ch_r_watermark = 0; in neo_set_no_input_flow_control()
211 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_input_flow_control()
212 ch->ch_t_tlevel = 16; in neo_set_no_input_flow_control()
214 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_input_flow_control()
215 ch->ch_r_tlevel = 16; in neo_set_no_input_flow_control()
217 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
223 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
224 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); in neo_set_no_output_flow_control()
233 if (ch->ch_c_iflag & IXOFF) in neo_set_no_output_flow_control()
239 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
242 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
244 /* Turn on table D, with 8 char hi/low watermarks */ in neo_set_no_output_flow_control()
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_output_flow_control()
247 ch->ch_r_watermark = 0; in neo_set_no_output_flow_control()
249 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_output_flow_control()
250 ch->ch_t_tlevel = 16; in neo_set_no_output_flow_control()
252 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_output_flow_control()
253 ch->ch_r_tlevel = 16; in neo_set_no_output_flow_control()
255 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
262 if (ch->ch_c_cflag & CRTSCTS) in neo_set_new_start_stop_chars()
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); in neo_set_new_start_stop_chars()
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_new_start_stop_chars()
269 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_new_start_stop_chars()
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_new_start_stop_chars()
272 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_new_start_stop_chars()
286 head = ch->ch_r_head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
287 tail = ch->ch_r_tail & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
290 linestatus = ch->ch_cached_lsr; in neo_copy_data_from_uart_to_queue()
291 ch->ch_cached_lsr = 0; in neo_copy_data_from_uart_to_queue()
294 qleft = tail - head - 1; in neo_copy_data_from_uart_to_queue()
305 if (!(ch->ch_flags & CH_FIFO_ENABLED)) in neo_copy_data_from_uart_to_queue()
308 total = readb(&ch->ch_neo_uart->rfifo); in neo_copy_data_from_uart_to_queue()
311 * EXAR chip bug - RX FIFO COUNT - Fudge factor. in neo_copy_data_from_uart_to_queue()
315 * The count can be any where from 0-3 bytes "off". in neo_copy_data_from_uart_to_queue()
318 total -= 3; in neo_copy_data_from_uart_to_queue()
334 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
345 n = min(((u32) total), (RQUEUESIZE - (u32) head)); in neo_copy_data_from_uart_to_queue()
349 * a problem with memcpy_fromio() with the Neo on the in neo_copy_data_from_uart_to_queue()
361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); in neo_copy_data_from_uart_to_queue()
372 memset(ch->ch_equeue + head, 0, n); in neo_copy_data_from_uart_to_queue()
376 total -= n; in neo_copy_data_from_uart_to_queue()
377 qleft -= n; in neo_copy_data_from_uart_to_queue()
378 ch->ch_rxcount += n; in neo_copy_data_from_uart_to_queue()
385 if (ch->ch_c_iflag & IGNBRK) in neo_copy_data_from_uart_to_queue()
398 linestatus |= readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
406 ch->ch_cached_lsr = linestatus; in neo_copy_data_from_uart_to_queue()
420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
442 jsm_dbg(READ, &ch->ch_bd->pci_dev, in neo_copy_data_from_uart_to_queue()
444 ch->ch_rqueue[tail], ch->ch_equeue[tail]); in neo_copy_data_from_uart_to_queue()
446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
447 ch->ch_err_overrun++; in neo_copy_data_from_uart_to_queue()
451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
452 ch->ch_equeue[head] = (u8) linestatus; in neo_copy_data_from_uart_to_queue()
454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", in neo_copy_data_from_uart_to_queue()
455 ch->ch_rqueue[head], ch->ch_equeue[head]); in neo_copy_data_from_uart_to_queue()
463 qleft--; in neo_copy_data_from_uart_to_queue()
464 ch->ch_rxcount++; in neo_copy_data_from_uart_to_queue()
470 ch->ch_r_head = head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
471 ch->ch_e_head = head & EQUEUEMASK; in neo_copy_data_from_uart_to_queue()
488 circ = &ch->uart_port.state->xmit; in neo_copy_data_from_queue_to_uart()
495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in neo_copy_data_from_queue_to_uart()
500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { in neo_copy_data_from_queue_to_uart()
501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_queue_to_uart()
503 ch->ch_cached_lsr |= lsrbits; in neo_copy_data_from_queue_to_uart()
504 if (ch->ch_cached_lsr & UART_LSR_THRE) { in neo_copy_data_from_queue_to_uart()
505 ch->ch_cached_lsr &= ~(UART_LSR_THRE); in neo_copy_data_from_queue_to_uart()
507 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); in neo_copy_data_from_queue_to_uart()
508 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, in neo_copy_data_from_queue_to_uart()
509 "Tx data: %x\n", circ->buf[circ->tail]); in neo_copy_data_from_queue_to_uart()
510 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
511 ch->ch_txcount++; in neo_copy_data_from_queue_to_uart()
519 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in neo_copy_data_from_queue_to_uart()
522 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; in neo_copy_data_from_queue_to_uart()
525 head = circ->head & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
526 tail = circ->tail & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
534 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; in neo_copy_data_from_queue_to_uart()
540 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); in neo_copy_data_from_queue_to_uart()
542 tail = (tail + s) & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
543 n -= s; in neo_copy_data_from_queue_to_uart()
544 ch->ch_txcount += s; in neo_copy_data_from_queue_to_uart()
549 circ->tail = tail & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
551 if (len_written >= ch->ch_t_tlevel) in neo_copy_data_from_queue_to_uart()
552 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_queue_to_uart()
555 uart_write_wakeup(&ch->uart_port); in neo_copy_data_from_queue_to_uart()
562 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
564 ch->ch_portnum, msignals); in neo_parse_modem()
571 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in neo_parse_modem()
573 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); in neo_parse_modem()
575 ch->ch_mistat |= UART_MSR_DCD; in neo_parse_modem()
577 ch->ch_mistat &= ~UART_MSR_DCD; in neo_parse_modem()
580 ch->ch_mistat |= UART_MSR_DSR; in neo_parse_modem()
582 ch->ch_mistat &= ~UART_MSR_DSR; in neo_parse_modem()
585 ch->ch_mistat |= UART_MSR_RI; in neo_parse_modem()
587 ch->ch_mistat &= ~UART_MSR_RI; in neo_parse_modem()
590 ch->ch_mistat |= UART_MSR_CTS; in neo_parse_modem()
592 ch->ch_mistat &= ~UART_MSR_CTS; in neo_parse_modem()
594 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
596 ch->ch_portnum, in neo_parse_modem()
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in neo_parse_modem()
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in neo_parse_modem()
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in neo_parse_modem()
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in neo_parse_modem()
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in neo_parse_modem()
602 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in neo_parse_modem()
611 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_assert_modem_signals()
614 neo_pci_posting_flush(ch->ch_bd); in neo_assert_modem_signals()
618 * Flush the WRITE FIFO on the Neo.
630 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
635 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
637 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_write()
645 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_flush_uart_write()
650 * Flush the READ FIFO on the Neo.
662 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
667 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
669 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_read()
685 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_clear_break()
688 if (ch->ch_flags & CH_BREAK_SENDING) { in neo_clear_break()
689 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_clear_break()
690 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_clear_break()
692 ch->ch_flags &= ~(CH_BREAK_SENDING); in neo_clear_break()
693 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_clear_break()
698 neo_pci_posting_flush(ch->ch_bd); in neo_clear_break()
700 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_clear_break()
716 if (port >= brd->maxports) in neo_parse_isr()
719 ch = brd->channels[port]; in neo_parse_isr()
726 isr = readb(&ch->ch_neo_uart->isr_fcr); in neo_parse_isr()
737 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", in neo_parse_isr()
741 /* Read data from uart -> queue */ in neo_parse_isr()
745 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
747 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
751 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_isr()
752 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
753 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_isr()
754 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
759 cause = readb(&ch->ch_neo_uart->xoffchar1); in neo_parse_isr()
761 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
770 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
773 if (brd->channels[port]->ch_flags & CH_STOP) { in neo_parse_isr()
774 ch->ch_flags &= ~(CH_STOP); in neo_parse_isr()
776 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
781 if (!(brd->channels[port]->ch_flags & CH_STOP)) { in neo_parse_isr()
782 ch->ch_flags |= CH_STOP; in neo_parse_isr()
783 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
786 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
790 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
798 cause = readb(&ch->ch_neo_uart->mcr); in neo_parse_isr()
801 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
804 ch->ch_mostat |= UART_MCR_RTS; in neo_parse_isr()
806 ch->ch_mostat &= ~(UART_MCR_RTS); in neo_parse_isr()
809 ch->ch_mostat |= UART_MCR_DTR; in neo_parse_isr()
811 ch->ch_mostat &= ~(UART_MCR_DTR); in neo_parse_isr()
813 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
817 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
819 spin_lock_irqsave(&ch->uart_port.lock, lock_flags); in neo_parse_isr()
820 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_parse_isr()
821 spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags); in neo_parse_isr()
834 if (port >= brd->maxports) in neo_parse_lsr()
837 ch = brd->channels[port]; in neo_parse_lsr()
841 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_parse_lsr()
843 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", in neo_parse_lsr()
846 ch->ch_cached_lsr |= linestatus; in neo_parse_lsr()
848 if (ch->ch_cached_lsr & UART_LSR_DR) { in neo_parse_lsr()
849 /* Read data from uart -> queue */ in neo_parse_lsr()
851 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
853 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
863 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
873 ch->ch_err_parity++; in neo_parse_lsr()
874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", in neo_parse_lsr()
879 ch->ch_err_frame++; in neo_parse_lsr()
880 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", in neo_parse_lsr()
885 ch->ch_err_break++; in neo_parse_lsr()
886 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
898 ch->ch_err_overrun++; in neo_parse_lsr()
899 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
905 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
906 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
907 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
909 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
913 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
914 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
915 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
917 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
934 bd = ch->ch_bd; in neo_param()
941 if ((ch->ch_c_cflag & CBAUD) == B0) { in neo_param()
942 ch->ch_r_head = ch->ch_r_tail = 0; in neo_param()
943 ch->ch_e_head = ch->ch_e_tail = 0; in neo_param()
948 ch->ch_flags |= (CH_BAUD0); in neo_param()
949 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in neo_param()
981 cflag = C_BAUD(ch->uart_port.state->port.tty); in neo_param()
990 if (ch->ch_flags & CH_BAUD0) in neo_param()
991 ch->ch_flags &= ~(CH_BAUD0); in neo_param()
994 if (ch->ch_c_cflag & PARENB) in neo_param()
997 if (!(ch->ch_c_cflag & PARODD)) in neo_param()
1000 if (ch->ch_c_cflag & CMSPAR) in neo_param()
1003 if (ch->ch_c_cflag & CSTOPB) in neo_param()
1006 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag)); in neo_param()
1008 ier = readb(&ch->ch_neo_uart->ier); in neo_param()
1009 uart_lcr = readb(&ch->ch_neo_uart->lcr); in neo_param()
1011 quot = ch->ch_bd->bd_dividend / baud; in neo_param()
1014 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); in neo_param()
1015 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); in neo_param()
1016 writeb((quot >> 8), &ch->ch_neo_uart->ier); in neo_param()
1017 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1021 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1023 if (ch->ch_c_cflag & CREAD) in neo_param()
1028 writeb(ier, &ch->ch_neo_uart->ier); in neo_param()
1033 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1035 else if (ch->ch_c_iflag & IXON) { in neo_param()
1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1045 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1047 else if (ch->ch_c_iflag & IXOFF) { in neo_param()
1049 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1062 writeb(1, &ch->ch_neo_uart->rfifo); in neo_param()
1063 ch->ch_r_tlevel = 1; in neo_param()
1069 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_param()
1076 * Neo specific interrupt handler.
1092 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); in neo_intr()
1095 * Read in "extended" IRQ information from the 32bit Neo register. in neo_intr()
1096 * Bits 0-7: What port triggered the interrupt. in neo_intr()
1097 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. in neo_intr()
1099 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); in neo_intr()
1101 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", in neo_intr()
1105 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1107 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1124 type = tmp >> (8 + (port * 3)); in neo_intr()
1131 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", in neo_intr()
1139 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1149 * RXRDY Time-out is cleared by reading data in the in neo_intr()
1154 if (port >= brd->nasync) in neo_intr()
1157 ch = brd->channels[port]; in neo_intr()
1164 spin_lock_irqsave(&ch->ch_lock, lock_flags2); in neo_intr()
1166 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); in neo_intr()
1207 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1214 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1216 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); in neo_intr()
1221 * Neo specific way of turning off the receiver.
1227 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_disable_receiver()
1229 writeb(tmp, &ch->ch_neo_uart->ier); in neo_disable_receiver()
1232 neo_pci_posting_flush(ch->ch_bd); in neo_disable_receiver()
1237 * Neo specific way of turning on the receiver.
1238 * Used as a way to un-enforce queue flow control when in
1243 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_enable_receiver()
1245 writeb(tmp, &ch->ch_neo_uart->ier); in neo_enable_receiver()
1248 neo_pci_posting_flush(ch->ch_bd); in neo_enable_receiver()
1256 if (ch->ch_startc != __DISABLED_CHAR) { in neo_send_start_character()
1257 ch->ch_xon_sends++; in neo_send_start_character()
1258 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); in neo_send_start_character()
1261 neo_pci_posting_flush(ch->ch_bd); in neo_send_start_character()
1270 if (ch->ch_stopc != __DISABLED_CHAR) { in neo_send_stop_character()
1271 ch->ch_xoff_sends++; in neo_send_stop_character()
1272 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); in neo_send_stop_character()
1275 neo_pci_posting_flush(ch->ch_bd); in neo_send_stop_character()
1284 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_init()
1285 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_init()
1286 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); in neo_uart_init()
1289 readb(&ch->ch_neo_uart->txrx); in neo_uart_init()
1290 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_uart_init()
1291 readb(&ch->ch_neo_uart->lsr); in neo_uart_init()
1292 readb(&ch->ch_neo_uart->msr); in neo_uart_init()
1294 ch->ch_flags |= CH_FIFO_ENABLED; in neo_uart_init()
1297 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_uart_init()
1306 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_off()
1309 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_off()
1315 u8 lsr = readb(&ch->ch_neo_uart->lsr); in neo_get_uart_bytes_left()
1318 ch->ch_cached_lsr |= lsr; in neo_get_uart_bytes_left()
1324 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_get_uart_bytes_left()
1341 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in neo_send_break()
1342 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_send_break()
1343 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_send_break()
1344 ch->ch_flags |= (CH_BREAK_SENDING); in neo_send_break()
1347 neo_pci_posting_flush(ch->ch_bd); in neo_send_break()
1364 writeb(c, &ch->ch_neo_uart->txrx); in neo_send_immediate_char()
1367 neo_pci_posting_flush(ch->ch_bd); in neo_send_immediate_char()