Lines Matching +full:rx +full:- +full:float +full:- +full:inactive
1 // SPDX-License-Identifier: GPL-2.0+
30 #include <linux/dma-mapping.h>
33 #include <linux/dma/imx-dma.h>
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define DRIVER_NAME "IMX-uart"
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 sport->ucr1 = val; in imx_uart_writel()
283 sport->ucr2 = val; in imx_uart_writel()
286 sport->ucr3 = val; in imx_uart_writel()
289 sport->ucr4 = val; in imx_uart_writel()
292 sport->ufcr = val; in imx_uart_writel()
297 writel(val, sport->port.membase + offset); in imx_uart_writel()
304 return sport->ucr1; in imx_uart_readl()
313 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
314 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
315 return sport->ucr2; in imx_uart_readl()
318 return sport->ucr3; in imx_uart_readl()
321 return sport->ucr4; in imx_uart_readl()
324 return sport->ufcr; in imx_uart_readl()
327 return readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->devdata->uts_reg; in imx_uart_uts_reg()
338 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
343 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
348 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
353 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
363 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
364 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
365 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
372 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
373 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
374 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
383 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
411 if (sport->dma_is_enabled) { in imx_uart_start_rx()
429 if (sport->tx_state == OFF) in imx_uart_stop_tx()
436 if (sport->dma_is_txing) in imx_uart_stop_tx()
453 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
454 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
455 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
457 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
458 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
459 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
466 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
467 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
470 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
473 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
481 sport->tx_state = OFF; in imx_uart_stop_tx()
484 sport->tx_state = OFF; in imx_uart_stop_tx()
498 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
517 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
519 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
527 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
529 if (sport->port.x_char) { in imx_uart_transmit_buffer()
531 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
532 sport->port.icount.tx++; in imx_uart_transmit_buffer()
533 sport->port.x_char = 0; in imx_uart_transmit_buffer()
537 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
538 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
542 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
545 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
550 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
563 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
565 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
566 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in imx_uart_transmit_buffer()
567 sport->port.icount.tx++; in imx_uart_transmit_buffer()
571 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
574 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
580 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
581 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
585 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
587 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
594 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
595 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
597 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
599 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
602 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
604 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
606 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
612 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
618 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
619 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
621 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
622 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
626 if (sport->dma_is_txing) in imx_uart_dma_tx()
633 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
635 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
636 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
637 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
639 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
641 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
642 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
643 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
646 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
654 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
659 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
660 desc->callback_param = sport; in imx_uart_dma_tx()
670 sport->dma_is_txing = 1; in imx_uart_dma_tx()
682 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
686 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
691 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
692 if (sport->tx_state == OFF) { in imx_uart_start_tx()
694 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
700 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in imx_uart_start_tx()
703 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
705 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
706 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
707 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
714 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
715 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
722 * tx-callback. in imx_uart_start_tx()
724 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
730 sport->tx_state = SEND; in imx_uart_start_tx()
733 sport->tx_state = SEND; in imx_uart_start_tx()
736 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
741 if (sport->dma_is_enabled) { in imx_uart_start_tx()
742 if (sport->port.x_char) { in imx_uart_start_tx()
743 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
744 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
752 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
766 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
777 spin_lock(&sport->port.lock); in imx_uart_rtsint()
781 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
790 spin_lock(&sport->port.lock); in imx_uart_txint()
792 spin_unlock(&sport->port.lock); in imx_uart_txint()
799 unsigned int rx, flg, ignored = 0; in __imx_uart_rxint() local
800 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
806 sport->port.icount.rx++; in __imx_uart_rxint()
808 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
813 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
817 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
820 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
821 if (rx & URXD_BRK) in __imx_uart_rxint()
822 sport->port.icount.brk++; in __imx_uart_rxint()
823 else if (rx & URXD_PRERR) in __imx_uart_rxint()
824 sport->port.icount.parity++; in __imx_uart_rxint()
825 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
826 sport->port.icount.frame++; in __imx_uart_rxint()
827 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
828 sport->port.icount.overrun++; in __imx_uart_rxint()
830 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
836 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
838 if (rx & URXD_BRK) in __imx_uart_rxint()
840 else if (rx & URXD_PRERR) in __imx_uart_rxint()
842 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
844 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
847 sport->port.sysrq = 0; in __imx_uart_rxint()
850 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
853 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
854 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
868 spin_lock(&sport->port.lock); in imx_uart_rxint()
872 spin_unlock(&sport->port.lock); in imx_uart_rxint()
895 if (sport->dte_mode) in imx_uart_get_hwmctrl()
910 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
915 sport->old_status = status; in imx_uart_mctrl_check()
918 sport->port.icount.rng++; in imx_uart_mctrl_check()
920 sport->port.icount.dsr++; in imx_uart_mctrl_check()
922 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
924 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
926 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
935 spin_lock(&sport->port.lock); in imx_uart_int()
947 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1000 sport->port.icount.overrun++; in imx_uart_int()
1005 spin_unlock(&sport->port.lock); in imx_uart_int()
1021 if (sport->dma_is_txing) in imx_uart_tx_empty()
1033 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1044 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1076 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1088 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1097 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1101 * This is our per-port timeout handler, for checking the
1109 if (sport->port.state) { in imx_uart_timeout()
1110 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1112 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1114 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1119 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1120 * [1] the RX DMA buffer is full.
1129 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1130 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1131 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1133 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1139 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1146 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1149 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1152 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1154 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1160 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1163 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1164 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1166 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1167 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1170 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1172 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1173 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1177 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1179 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1180 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1184 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1186 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1188 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1189 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1195 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1201 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1202 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1203 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1207 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1208 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1210 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1213 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1214 return -EINVAL; in imx_uart_start_rx_dma()
1218 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1223 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1224 return -EINVAL; in imx_uart_start_rx_dma()
1226 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1227 desc->callback_param = sport; in imx_uart_start_rx_dma()
1229 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1230 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1231 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1238 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1245 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1247 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1249 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1253 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1256 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1262 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1286 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1287 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1288 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1289 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1290 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1291 kfree(sport->rx_buf); in imx_uart_dma_exit()
1292 sport->rx_buf = NULL; in imx_uart_dma_exit()
1295 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1296 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1297 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1298 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1305 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1308 /* Prepare for RX : */ in imx_uart_dma_init()
1309 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1310 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1312 ret = -EINVAL; in imx_uart_dma_init()
1317 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1320 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1321 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1323 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1327 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1328 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1329 if (!sport->rx_buf) { in imx_uart_dma_init()
1330 ret = -ENOMEM; in imx_uart_dma_init()
1333 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1336 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1337 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1339 ret = -EINVAL; in imx_uart_dma_init()
1344 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1347 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1370 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1384 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1387 /* half the RX buffer size */
1398 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1401 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1403 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1424 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1432 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1443 if (sport->have_rtscts) in imx_uart_startup()
1451 if (sport->inverted_rx) in imx_uart_startup()
1459 if (sport->inverted_tx) in imx_uart_startup()
1465 if (sport->dte_mode) in imx_uart_startup()
1473 if (!sport->have_rtscts) in imx_uart_startup()
1476 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1486 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1501 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1512 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1513 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1514 if (sport->dma_is_txing) { in imx_uart_shutdown()
1515 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1516 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1517 sport->dma_is_txing = 0; in imx_uart_shutdown()
1519 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1520 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1521 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1523 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1526 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1530 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1534 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1536 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1540 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1545 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1551 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1561 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1563 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1564 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1571 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1575 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1578 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1579 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1580 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1588 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1596 * and UTS[6-3]". in imx_uart_flush_buffer()
1610 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1627 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1635 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1636 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1637 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1638 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1642 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1647 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1650 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1660 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1663 if (!sport->have_rtscts) in imx_uart_set_termios()
1664 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1666 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1672 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1677 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1680 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1686 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1688 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1690 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1692 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1696 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1697 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1698 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1699 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1700 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1705 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1706 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1707 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1708 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1709 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1714 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1715 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1718 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1719 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1722 * Update the per-port timeout. in imx_uart_set_termios()
1724 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1726 /* custom-baudrate handling */ in imx_uart_set_termios()
1727 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1729 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1731 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1737 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1740 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1746 num -= 1; in imx_uart_set_termios()
1747 denom -= 1; in imx_uart_set_termios()
1770 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1775 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1776 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1778 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1785 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1796 sport->port.type = PORT_IMX; in imx_uart_config_port()
1810 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1811 ret = -EINVAL; in imx_uart_verify_port()
1812 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1813 ret = -EINVAL; in imx_uart_verify_port()
1814 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1815 ret = -EINVAL; in imx_uart_verify_port()
1816 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1817 ret = -EINVAL; in imx_uart_verify_port()
1818 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1819 ret = -EINVAL; in imx_uart_verify_port()
1820 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1821 ret = -EINVAL; in imx_uart_verify_port()
1822 if (ser->hub6 != 0) in imx_uart_verify_port()
1823 ret = -EINVAL; in imx_uart_verify_port()
1836 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1839 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1841 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1845 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1850 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1873 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1914 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1915 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1916 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1917 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1918 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1922 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1929 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1930 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1931 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1979 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
1985 if (sport->port.sysrq) in imx_uart_console_write()
1988 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1990 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2007 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2018 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2058 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2060 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2066 * without need of float support or long long division, in imx_uart_console_get_options()
2079 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2099 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2100 co->index = 0; in imx_uart_console_setup()
2101 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2103 return -ENODEV; in imx_uart_console_setup()
2106 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2117 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2120 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2124 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2126 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2135 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2137 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2138 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2151 .index = -1,
2176 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2177 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2178 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2179 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2189 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2190 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2191 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2192 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2205 /* Default RX DMA buffer configuration */
2211 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2220 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2222 return -ENOMEM; in imx_uart_probe()
2224 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2228 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2231 sport->port.line = ret; in imx_uart_probe()
2233 if (of_get_property(np, "uart-has-rtscts", NULL) || in imx_uart_probe()
2234 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) in imx_uart_probe()
2235 sport->have_rtscts = 1; in imx_uart_probe()
2237 if (of_get_property(np, "fsl,dte-mode", NULL)) in imx_uart_probe()
2238 sport->dte_mode = 1; in imx_uart_probe()
2240 if (of_get_property(np, "rts-gpios", NULL)) in imx_uart_probe()
2241 sport->have_rtsgpio = 1; in imx_uart_probe()
2243 if (of_get_property(np, "fsl,inverted-tx", NULL)) in imx_uart_probe()
2244 sport->inverted_tx = 1; in imx_uart_probe()
2246 if (of_get_property(np, "fsl,inverted-rx", NULL)) in imx_uart_probe()
2247 sport->inverted_rx = 1; in imx_uart_probe()
2249 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2250 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2251 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2253 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2254 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2257 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2258 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2259 sport->port.line); in imx_uart_probe()
2260 return -EINVAL; in imx_uart_probe()
2264 base = devm_ioremap_resource(&pdev->dev, res); in imx_uart_probe()
2274 sport->port.dev = &pdev->dev; in imx_uart_probe()
2275 sport->port.mapbase = res->start; in imx_uart_probe()
2276 sport->port.membase = base; in imx_uart_probe()
2277 sport->port.type = PORT_IMX; in imx_uart_probe()
2278 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2279 sport->port.irq = rxirq; in imx_uart_probe()
2280 sport->port.fifosize = 32; in imx_uart_probe()
2281 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2282 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2283 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2285 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2286 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2288 sport->port.rs485_supported = imx_no_rs485; in imx_uart_probe()
2289 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2290 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2292 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2293 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2294 return PTR_ERR(sport->gpios); in imx_uart_probe()
2296 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2297 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2298 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2299 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2303 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2304 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2305 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2306 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2310 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2313 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2315 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2320 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2321 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2322 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2323 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2324 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2326 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2328 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2332 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2333 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2334 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2341 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2342 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2343 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2344 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2345 dev_err(&pdev->dev, in imx_uart_probe()
2346 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2353 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2384 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2386 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2387 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2388 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2389 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2396 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2397 dev_name(&pdev->dev), sport); in imx_uart_probe()
2399 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2404 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2405 dev_name(&pdev->dev), sport); in imx_uart_probe()
2407 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2412 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2413 dev_name(&pdev->dev), sport); in imx_uart_probe()
2415 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2420 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2421 dev_name(&pdev->dev), sport); in imx_uart_probe()
2423 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2428 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2432 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2439 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2446 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2447 if (!sport->context_saved) { in imx_uart_restore_context()
2448 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2452 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2453 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2454 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2455 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2456 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2457 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2458 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2459 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2460 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2461 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2462 sport->context_saved = false; in imx_uart_restore_context()
2463 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2471 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2472 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2473 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2474 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2475 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2476 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2477 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2478 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2479 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2480 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2481 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2482 sport->context_saved = true; in imx_uart_save_context()
2483 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2499 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2517 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2531 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2545 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2546 disable_irq(sport->port.irq); in imx_uart_suspend()
2548 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2565 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2566 enable_irq(sport->port.irq); in imx_uart_resume()
2568 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2577 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2579 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2586 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2588 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2611 .name = "imx-uart",
2643 MODULE_ALIAS("platform:imx-uart");