Lines Matching refs:sport
334 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) in is_layerscape_lpuart() argument
336 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
337 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
340 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) in is_imx7ulp_lpuart() argument
342 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
345 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) in is_imx8qxp_lpuart() argument
347 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
375 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) in __lpuart_enable_clks() argument
380 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
384 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
386 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
390 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
391 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
397 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) in lpuart_get_baud_clk_rate() argument
399 if (is_imx8qxp_lpuart(sport)) in lpuart_get_baud_clk_rate()
400 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
402 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
442 static void lpuart_dma_tx(struct lpuart_port *sport) in lpuart_dma_tx() argument
444 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
445 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
446 struct device *dev = sport->port.dev; in lpuart_dma_tx()
447 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
450 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
453 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
456 sport->dma_tx_nents = 1; in lpuart_dma_tx()
457 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
459 sport->dma_tx_nents = 2; in lpuart_dma_tx()
466 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
473 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
476 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
477 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
483 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
484 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
485 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
486 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
497 struct lpuart_port *sport = arg; in lpuart_dma_tx_complete() local
498 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
499 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
500 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
503 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
504 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
505 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
512 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); in lpuart_dma_tx_complete()
514 sport->port.icount.tx += sport->dma_tx_bytes; in lpuart_dma_tx_complete()
515 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
516 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
519 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
521 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
522 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
526 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
528 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
529 lpuart_dma_tx(sport); in lpuart_dma_tx_complete()
531 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
534 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) in lpuart_dma_datareg_addr() argument
536 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
538 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
540 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
542 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
547 struct lpuart_port *sport = container_of(port, in lpuart_dma_tx_request() local
552 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); in lpuart_dma_tx_request()
556 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
559 dev_err(sport->port.dev, in lpuart_dma_tx_request()
567 static bool lpuart_is_32(struct lpuart_port *sport) in lpuart_is_32() argument
569 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
570 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
575 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_flush_buffer() local
576 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
579 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
580 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
581 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
582 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
583 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
588 if (lpuart_is_32(sport)) { in lpuart_flush_buffer()
589 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
591 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
593 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
595 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
617 struct lpuart_port *sport = container_of(port, in lpuart_poll_init() local
622 sport->port.fifosize = 0; in lpuart_poll_init()
624 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
626 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
628 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
631 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
635 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
638 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
639 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
640 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
643 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
644 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
647 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
648 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
671 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_poll_init() local
674 sport->port.fifosize = 0; in lpuart32_poll_init()
676 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
679 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
681 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
684 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
687 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
690 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
691 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
692 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
696 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
697 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
717 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) in lpuart_transmit_buffer() argument
719 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_transmit_buffer()
721 if (sport->port.x_char) { in lpuart_transmit_buffer()
722 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_transmit_buffer()
723 sport->port.icount.tx++; in lpuart_transmit_buffer()
724 sport->port.x_char = 0; in lpuart_transmit_buffer()
728 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart_transmit_buffer()
729 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
734 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
735 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
737 sport->port.icount.tx++; in lpuart_transmit_buffer()
741 uart_write_wakeup(&sport->port); in lpuart_transmit_buffer()
744 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
747 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) in lpuart32_transmit_buffer() argument
749 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
752 if (sport->port.x_char) { in lpuart32_transmit_buffer()
753 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
754 sport->port.icount.tx++; in lpuart32_transmit_buffer()
755 sport->port.x_char = 0; in lpuart32_transmit_buffer()
759 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
760 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
764 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
767 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
768 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
770 sport->port.icount.tx++; in lpuart32_transmit_buffer()
771 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
777 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
780 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
785 struct lpuart_port *sport = container_of(port, in lpuart_start_tx() local
792 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
794 lpuart_dma_tx(sport); in lpuart_start_tx()
797 lpuart_transmit_buffer(sport); in lpuart_start_tx()
803 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_start_tx() local
806 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
808 lpuart_dma_tx(sport); in lpuart32_start_tx()
814 lpuart32_transmit_buffer(sport); in lpuart32_start_tx()
821 struct lpuart_port *sport = container_of(port, in lpuart_tx_empty() local
826 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
837 struct lpuart_port *sport = container_of(port, in lpuart32_tx_empty() local
842 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
851 static void lpuart_txint(struct lpuart_port *sport) in lpuart_txint() argument
853 spin_lock(&sport->port.lock); in lpuart_txint()
854 lpuart_transmit_buffer(sport); in lpuart_txint()
855 spin_unlock(&sport->port.lock); in lpuart_txint()
858 static void lpuart_rxint(struct lpuart_port *sport) in lpuart_rxint() argument
861 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
864 spin_lock(&sport->port.lock); in lpuart_rxint()
866 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
868 sport->port.icount.rx++; in lpuart_rxint()
873 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
874 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
876 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
881 sport->port.icount.parity++; in lpuart_rxint()
883 sport->port.icount.frame++; in lpuart_rxint()
888 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
894 sr &= sport->port.read_status_mask; in lpuart_rxint()
904 sport->port.sysrq = 0; in lpuart_rxint()
908 sport->port.icount.buf_overrun++; in lpuart_rxint()
913 sport->port.icount.overrun += overrun; in lpuart_rxint()
919 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
920 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
923 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
928 static void lpuart32_txint(struct lpuart_port *sport) in lpuart32_txint() argument
930 spin_lock(&sport->port.lock); in lpuart32_txint()
931 lpuart32_transmit_buffer(sport); in lpuart32_txint()
932 spin_unlock(&sport->port.lock); in lpuart32_txint()
935 static void lpuart32_rxint(struct lpuart_port *sport) in lpuart32_rxint() argument
938 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
942 spin_lock(&sport->port.lock); in lpuart32_rxint()
944 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
946 sport->port.icount.rx++; in lpuart32_rxint()
951 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
952 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
961 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
964 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
969 sport->port.icount.parity++; in lpuart32_rxint()
972 sport->port.icount.brk++; in lpuart32_rxint()
974 sport->port.icount.frame++; in lpuart32_rxint()
978 sport->port.icount.overrun++; in lpuart32_rxint()
980 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
986 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1001 if (sport->is_cs7) in lpuart32_rxint()
1005 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1009 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1016 struct lpuart_port *sport = dev_id; in lpuart_int() local
1019 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1022 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1023 readb(sport->port.membase + UARTDR); in lpuart_int()
1024 uart_handle_break(&sport->port); in lpuart_int()
1026 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1030 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1031 lpuart_rxint(sport); in lpuart_int()
1033 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1034 lpuart_txint(sport); in lpuart_int()
1041 struct lpuart_port *sport = dev_id; in lpuart32_int() local
1044 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1045 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1048 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1049 lpuart32_rxint(sport); in lpuart32_int()
1051 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1052 lpuart32_txint(sport); in lpuart32_int()
1054 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1069 static void lpuart_handle_sysrq(struct lpuart_port *sport) in lpuart_handle_sysrq() argument
1071 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1075 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1076 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1083 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1100 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) in lpuart_copy_rx_to_tty() argument
1102 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1105 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1106 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1110 if (lpuart_is_32(sport)) { in lpuart_copy_rx_to_tty()
1111 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1115 lpuart32_read(&sport->port, UARTDATA); in lpuart_copy_rx_to_tty()
1118 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1120 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1123 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1129 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1131 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1134 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1137 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1139 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1149 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1152 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1154 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1158 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1162 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1164 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1166 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1168 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1169 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1174 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1184 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1185 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1190 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1191 lpuart_handle_sysrq(sport); in lpuart_copy_rx_to_tty()
1208 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1211 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1213 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1215 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1222 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1224 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1226 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1229 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1233 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1236 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1239 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1244 struct lpuart_port *sport = arg; in lpuart_dma_rx_complete() local
1246 lpuart_copy_rx_to_tty(sport); in lpuart_dma_rx_complete()
1251 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); in lpuart_timer_func() local
1253 lpuart_copy_rx_to_tty(sport); in lpuart_timer_func()
1256 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) in lpuart_start_rx_dma() argument
1259 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1261 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1264 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1272 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1273 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); in lpuart_start_rx_dma()
1274 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1275 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1277 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1281 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1282 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1286 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1290 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); in lpuart_start_rx_dma()
1297 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1302 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1303 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1304 sport->rx_sgl.length, in lpuart_start_rx_dma()
1305 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1308 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1309 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1313 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1314 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1315 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1318 if (lpuart_is_32(sport)) { in lpuart_start_rx_dma()
1319 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1321 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1323 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1324 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1332 struct lpuart_port *sport = container_of(port, in lpuart_dma_rx_free() local
1334 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1337 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1338 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1339 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1340 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1341 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1342 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1348 struct lpuart_port *sport = container_of(port, in lpuart_config_rs485() local
1351 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1353 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1371 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1378 struct lpuart_port *sport = container_of(port, in lpuart32_config_rs485() local
1381 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1383 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1401 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1481 static void lpuart_setup_watermark(struct lpuart_port *sport) in lpuart_setup_watermark() argument
1486 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1490 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1492 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1494 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1498 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1501 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1502 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1503 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1506 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1507 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1510 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1513 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) in lpuart_setup_watermark_enable() argument
1517 lpuart_setup_watermark(sport); in lpuart_setup_watermark_enable()
1519 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1521 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1524 static void lpuart32_setup_watermark(struct lpuart_port *sport) in lpuart32_setup_watermark() argument
1529 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1533 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1536 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1539 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1543 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1546 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1549 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) in lpuart32_setup_watermark_enable() argument
1553 lpuart32_setup_watermark(sport); in lpuart32_setup_watermark_enable()
1555 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1557 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1560 static void rx_dma_timer_init(struct lpuart_port *sport) in rx_dma_timer_init() argument
1562 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1563 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1564 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1567 static void lpuart_request_dma(struct lpuart_port *sport) in lpuart_request_dma() argument
1569 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1570 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1571 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1573 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1574 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1577 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1578 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1579 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1581 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1582 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1586 static void lpuart_tx_dma_startup(struct lpuart_port *sport) in lpuart_tx_dma_startup() argument
1591 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1594 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1597 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1601 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1602 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1603 if (lpuart_is_32(sport)) { in lpuart_tx_dma_startup()
1604 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1605 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1608 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1609 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1615 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1618 static void lpuart_rx_dma_startup(struct lpuart_port *sport) in lpuart_rx_dma_startup() argument
1623 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1626 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1629 ret = lpuart_start_rx_dma(sport); in lpuart_rx_dma_startup()
1634 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1635 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1636 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1638 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1639 rx_dma_timer_init(sport); in lpuart_rx_dma_startup()
1641 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1642 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1644 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1650 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1655 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_startup() local
1660 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1662 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1664 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1666 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1669 lpuart_request_dma(sport); in lpuart_startup()
1671 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_startup()
1673 lpuart_setup_watermark_enable(sport); in lpuart_startup()
1675 lpuart_rx_dma_startup(sport); in lpuart_startup()
1676 lpuart_tx_dma_startup(sport); in lpuart_startup()
1678 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_startup()
1683 static void lpuart32_configure(struct lpuart_port *sport) in lpuart32_configure() argument
1687 if (sport->lpuart_dma_rx_use) { in lpuart32_configure()
1689 temp = lpuart32_read(&sport->port, UARTWATER); in lpuart32_configure()
1691 lpuart32_write(&sport->port, temp, UARTWATER); in lpuart32_configure()
1693 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1694 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1696 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1698 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1703 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_startup() local
1708 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1710 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1712 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1714 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1722 if (is_layerscape_lpuart(sport)) { in lpuart32_startup()
1723 sport->rxfifo_size = 16; in lpuart32_startup()
1724 sport->txfifo_size = 16; in lpuart32_startup()
1725 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1728 lpuart_request_dma(sport); in lpuart32_startup()
1730 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_startup()
1732 lpuart32_setup_watermark_enable(sport); in lpuart32_startup()
1734 lpuart_rx_dma_startup(sport); in lpuart32_startup()
1735 lpuart_tx_dma_startup(sport); in lpuart32_startup()
1737 lpuart32_configure(sport); in lpuart32_startup()
1739 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_startup()
1743 static void lpuart_dma_shutdown(struct lpuart_port *sport) in lpuart_dma_shutdown() argument
1745 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1746 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_shutdown()
1747 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1748 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1751 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1752 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1753 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1754 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1755 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_dma_shutdown()
1757 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1760 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1761 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1762 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1763 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1768 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_shutdown() local
1782 lpuart_dma_shutdown(sport); in lpuart_shutdown()
1787 struct lpuart_port *sport = in lpuart32_shutdown() local
1802 lpuart_dma_shutdown(sport); in lpuart32_shutdown()
1809 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_set_termios() local
1816 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1817 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1818 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1819 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1820 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1821 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1853 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
1897 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1898 del_timer_sync(&sport->lpuart_timer); in lpuart_set_termios()
1899 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
1902 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
1904 sport->port.read_status_mask = 0; in lpuart_set_termios()
1906 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
1908 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1911 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
1913 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
1915 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1921 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
1928 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
1932 sport->port.membase + UARTCR2); in lpuart_set_termios()
1934 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
1935 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
1940 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1941 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1942 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1943 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
1944 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1945 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1948 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1950 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1951 if (!lpuart_start_rx_dma(sport)) in lpuart_set_termios()
1952 rx_dma_timer_init(sport); in lpuart_set_termios()
1954 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
1957 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
2036 static void lpuart32_serial_setbrg(struct lpuart_port *sport, in lpuart32_serial_setbrg() argument
2039 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2040 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2041 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2049 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_set_termios() local
2055 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2056 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2057 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2058 sport->is_cs7 = false; in lpuart32_set_termios()
2090 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2134 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2135 del_timer_sync(&sport->lpuart_timer); in lpuart32_set_termios()
2136 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2139 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2141 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2143 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2145 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2148 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2150 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2152 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2158 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2165 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2166 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2169 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2172 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2173 lpuart32_serial_setbrg(sport, baud); in lpuart32_set_termios()
2174 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2175 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2179 sport->is_cs7 = true; in lpuart32_set_termios()
2181 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2182 if (!lpuart_start_rx_dma(sport)) in lpuart32_set_termios()
2183 rx_dma_timer_init(sport); in lpuart32_set_termios()
2185 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2188 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2298 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write() local
2304 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2306 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2309 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2312 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2314 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2317 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2319 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2322 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2328 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write() local
2334 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2336 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2339 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2342 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2344 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2347 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2349 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2352 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2360 lpuart_console_get_options(struct lpuart_port *sport, int *baud, in lpuart_console_get_options() argument
2366 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2373 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2388 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2390 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2394 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2397 uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_console_get_options()
2404 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2409 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, in lpuart32_console_get_options() argument
2415 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2422 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2437 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2443 uartclk = lpuart_get_baud_clk_rate(sport); in lpuart32_console_get_options()
2450 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2456 struct lpuart_port *sport; in lpuart_console_setup() local
2470 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2471 if (sport == NULL) in lpuart_console_setup()
2477 if (lpuart_is_32(sport)) in lpuart_console_setup()
2478 lpuart32_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2480 lpuart_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2482 if (lpuart_is_32(sport)) in lpuart_console_setup()
2483 lpuart32_setup_watermark(sport); in lpuart_console_setup()
2485 lpuart_setup_watermark(sport); in lpuart_console_setup()
2487 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2613 static int lpuart_global_reset(struct lpuart_port *sport) in lpuart_global_reset() argument
2615 struct uart_port *port = &sport->port; in lpuart_global_reset()
2621 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2623 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2627 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { in lpuart_global_reset()
2634 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart_global_reset()
2637 dev_warn(sport->port.dev, in lpuart_global_reset()
2639 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2657 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2665 struct lpuart_port *sport; in lpuart_probe() local
2670 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2671 if (!sport) in lpuart_probe()
2675 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
2676 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2677 return PTR_ERR(sport->port.membase); in lpuart_probe()
2679 sport->port.membase += sdata->reg_off; in lpuart_probe()
2680 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2681 sport->port.dev = &pdev->dev; in lpuart_probe()
2682 sport->port.type = PORT_LPUART; in lpuart_probe()
2683 sport->devtype = sdata->devtype; in lpuart_probe()
2687 sport->port.irq = ret; in lpuart_probe()
2688 sport->port.iotype = sdata->iotype; in lpuart_probe()
2689 if (lpuart_is_32(sport)) in lpuart_probe()
2690 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2692 sport->port.ops = &lpuart_pops; in lpuart_probe()
2693 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2694 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2696 if (lpuart_is_32(sport)) in lpuart_probe()
2697 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2699 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2700 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2702 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2703 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2704 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2709 sport->baud_clk = NULL; in lpuart_probe()
2710 if (is_imx8qxp_lpuart(sport)) { in lpuart_probe()
2711 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2712 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2713 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2728 sport->port.line = ret; in lpuart_probe()
2730 ret = lpuart_enable_clks(sport); in lpuart_probe()
2733 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2735 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2737 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2739 if (lpuart_is_32(sport)) { in lpuart_probe()
2747 ret = lpuart_global_reset(sport); in lpuart_probe()
2751 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2755 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2759 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2760 DRIVER_NAME, sport); in lpuart_probe()
2767 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2771 lpuart_disable_clks(sport); in lpuart_probe()
2777 struct lpuart_port *sport = platform_get_drvdata(pdev); in lpuart_remove() local
2779 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2781 lpuart_disable_clks(sport); in lpuart_remove()
2783 if (sport->dma_tx_chan) in lpuart_remove()
2784 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2786 if (sport->dma_rx_chan) in lpuart_remove()
2787 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2794 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_suspend() local
2798 if (lpuart_is_32(sport)) { in lpuart_suspend()
2800 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
2802 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
2805 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
2807 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
2810 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
2813 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend()
2815 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
2824 del_timer_sync(&sport->lpuart_timer); in lpuart_suspend()
2825 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
2829 if (lpuart_is_32(sport)) { in lpuart_suspend()
2830 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
2831 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
2834 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
2835 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
2839 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
2840 sport->dma_tx_in_progress = false; in lpuart_suspend()
2841 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_suspend()
2844 if (sport->port.suspended && !irq_wake) in lpuart_suspend()
2845 lpuart_disable_clks(sport); in lpuart_suspend()
2852 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_resume() local
2853 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_resume()
2855 if (sport->port.suspended && !irq_wake) in lpuart_resume()
2856 lpuart_enable_clks(sport); in lpuart_resume()
2858 if (lpuart_is_32(sport)) in lpuart_resume()
2859 lpuart32_setup_watermark_enable(sport); in lpuart_resume()
2861 lpuart_setup_watermark_enable(sport); in lpuart_resume()
2863 if (sport->lpuart_dma_rx_use) { in lpuart_resume()
2865 if (!lpuart_start_rx_dma(sport)) in lpuart_resume()
2866 rx_dma_timer_init(sport); in lpuart_resume()
2868 sport->lpuart_dma_rx_use = false; in lpuart_resume()
2872 lpuart_tx_dma_startup(sport); in lpuart_resume()
2874 if (lpuart_is_32(sport)) in lpuart_resume()
2875 lpuart32_configure(sport); in lpuart_resume()
2877 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()