Lines Matching +full:max +full:- +full:channels +full:- +full:clocked
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
30 * > 0 - number of ports
31 * = 0 - use board->num_ports
32 * < 0 - error
80 "Please send the output of lspci -vv, this\n" in moan_device()
83 "modem board to <linux-serial@vger.kernel.org>.\n", in moan_device()
84 str, dev->vendor, dev->device, in moan_device()
85 dev->subsystem_vendor, dev->subsystem_device); in moan_device()
92 struct pci_dev *dev = priv->dev; in setup_port()
95 return -EINVAL; in setup_port()
99 return -ENOMEM; in setup_port()
101 port->port.iotype = UPIO_MEM; in setup_port()
102 port->port.iobase = 0; in setup_port()
103 port->port.mapbase = pci_resource_start(dev, bar) + offset; in setup_port()
104 port->port.membase = pcim_iomap_table(dev)[bar] + offset; in setup_port()
105 port->port.regshift = regshift; in setup_port()
107 port->port.iotype = UPIO_PORT; in setup_port()
108 port->port.iobase = pci_resource_start(dev, bar) + offset; in setup_port()
109 port->port.mapbase = 0; in setup_port()
110 port->port.membase = NULL; in setup_port()
111 port->port.regshift = 0; in setup_port()
117 * ADDI-DATA GmbH communication cards <info@addi-data.com>
123 unsigned int bar = 0, offset = board->first_offset; in addidata_apci7800_setup()
124 bar = FL_GET_BASE(board->flags); in addidata_apci7800_setup()
127 offset += idx * board->uart_offset; in addidata_apci7800_setup()
130 offset += ((idx - 2) * board->uart_offset); in addidata_apci7800_setup()
133 offset += ((idx - 4) * board->uart_offset); in addidata_apci7800_setup()
136 offset += ((idx - 6) * board->uart_offset); in addidata_apci7800_setup()
139 return setup_port(priv, port, bar, offset, board->reg_shift); in addidata_apci7800_setup()
144 * Not that ugly ;) -- HW
150 unsigned int bar, offset = board->first_offset; in afavlab_setup()
152 bar = FL_GET_BASE(board->flags); in afavlab_setup()
157 offset += (idx - 4) * board->uart_offset; in afavlab_setup()
160 return setup_port(priv, port, bar, offset, board->reg_shift); in afavlab_setup()
165 * different versions. N-class, L2000 and A500 have two Diva chips, each
174 switch (dev->subsystem_device) { in pci_hp_diva_init()
205 unsigned int offset = board->first_offset; in pci_hp_diva_setup()
206 unsigned int bar = FL_GET_BASE(board->flags); in pci_hp_diva_setup()
208 switch (priv->dev->subsystem_device) { in pci_hp_diva_setup()
223 offset += idx * board->uart_offset; in pci_hp_diva_setup()
225 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_hp_diva_setup()
235 if (!(dev->subsystem_device & 0x1000)) in pci_inteli960ni_init()
236 return -ENODEV; in pci_inteli960ni_init()
242 return -ENODEV; in pci_inteli960ni_init()
264 if (dev->vendor == PCI_VENDOR_ID_PANACOM || in pci_plx9050_init()
265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) in pci_plx9050_init()
268 if ((dev->vendor == PCI_VENDOR_ID_PLX) && in pci_plx9050_init()
269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) in pci_plx9050_init()
284 return -ENOMEM; in pci_plx9050_init()
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
374 unsigned int bar, offset = board->first_offset; in sbs_setup()
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ in sbs_setup()
380 offset += idx * board->uart_offset; in sbs_setup()
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ in sbs_setup()
383 offset += idx * board->uart_offset + 0xC00; in sbs_setup()
384 } else /* we have only 8 ports on PMC-OCTALPRO */ in sbs_setup()
387 return setup_port(priv, port, bar, offset, board->reg_shift); in sbs_setup()
397 /* global control register offset for SBS PMC-OctalPro */
407 return -ENOMEM; in sbs_init()
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ in sbs_init()
413 /* Set bit-2 (INTENABLE) of Control Register */ in sbs_init()
421 * Disables the global interrupt of PMC-OctalPro
437 * the UART clocking frequency. Each UART can be clocked independently
440 * version of serial driver doesn't support differently clocked UART's
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
470 switch (dev->device & 0xfff8) { in pci_siig10x_init()
484 return -ENOMEM; in pci_siig10x_init()
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || in pci_siig20x_init()
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { in pci_siig20x_init()
514 unsigned int type = dev->device & 0xff00; in pci_siig_init()
522 return -ENODEV; in pci_siig_init()
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; in pci_siig_setup()
533 offset = (idx - 4) * 8; in pci_siig_setup()
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) in pci_timedia_probe()
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { in pci_timedia_probe()
592 dev->subsystem_device); in pci_timedia_probe()
593 return -ENODEV; in pci_timedia_probe()
607 if (dev->subsystem_device == ids[j]) in pci_timedia_init()
615 * Ugh, this is ugly as all hell --- TYT
622 unsigned int bar = 0, offset = board->first_offset; in pci_timedia_setup()
629 offset = board->uart_offset; in pci_timedia_setup()
636 offset = board->uart_offset; in pci_timedia_setup()
642 bar = idx - 2; in pci_timedia_setup()
645 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_timedia_setup()
656 unsigned int bar, offset = board->first_offset; in titan_400l_800l_setup()
667 offset = (idx - 2) * board->uart_offset; in titan_400l_800l_setup()
670 return setup_port(priv, port, bar, offset, board->reg_shift); in titan_400l_800l_setup()
691 return -ENOMEM; in pci_ni8420_init()
722 return -ENOMEM; in pci_ni8430_init()
729 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); in pci_ni8430_init()
757 struct pci_dev *dev = priv->dev; in pci_ni8430_setup()
759 unsigned int bar, offset = board->first_offset; in pci_ni8430_setup()
761 if (idx >= board->num_ports) in pci_ni8430_setup()
764 bar = FL_GET_BASE(board->flags); in pci_ni8430_setup()
765 offset += idx * board->uart_offset; in pci_ni8430_setup()
769 return -ENOMEM; in pci_ni8430_setup()
777 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_ni8430_setup()
786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && in pci_netmos_9900_setup()
787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { in pci_netmos_9900_setup()
793 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
802 * 9900 has varying capabilities and can cascade to sub-controllers
809 unsigned int c = dev->class; in pci_netmos_9900_numports()
818 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { in pci_netmos_9900_numports()
825 sub_serports = dev->subsystem_device & 0xf; in pci_netmos_9900_numports()
840 unsigned int num_serial = dev->subsystem_device & 0xf; in pci_netmos_init()
842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || in pci_netmos_init()
843 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) in pci_netmos_init()
846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in pci_netmos_init()
847 dev->subsystem_device == 0x0299) in pci_netmos_init()
850 switch (dev->device) { /* FALLTHROUGH on all */ in pci_netmos_init()
864 return -ENODEV; in pci_netmos_init()
889 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 /* I/O space size (bits 26-24; 32 bytes = 101b) */
906 /* search for the base-ioport */ in pci_ite887x_init()
911 /* write POSIO0R - speed | size | ioport */ in pci_ite887x_init()
915 /* write INTCBAR - ioport */ in pci_ite887x_init()
923 release_region(iobase->start, ITE_887x_IOSIZE); in pci_ite887x_init()
929 return -ENODEV; in pci_ite887x_init()
933 type = inb(iobase->start + 0x18) & 0x0f; in pci_ite887x_init()
951 ret = -ENODEV; in pci_ite887x_init()
973 miscr &= ~(0xf << (12 - 4 * i)); in pci_ite887x_init()
975 miscr |= 1 << (23 - i); in pci_ite887x_init()
982 release_region(iobase->start, ITE_887x_IOSIZE); in pci_ite887x_init()
991 /* the ioport is bit 0-15 in POSIO0R */ in pci_ite887x_exit()
1007 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && in pci_oxsemi_tornado_p()
1008 (dev->device & 0xf000) != 0xc000) in pci_oxsemi_tornado_p()
1012 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && in pci_oxsemi_tornado_p()
1013 (dev->device & 0xf000) != 0xe000) in pci_oxsemi_tornado_p()
1033 return -ENOMEM; in pci_oxsemi_tornado_init()
1041 dev->vendor == PCI_VENDOR_ID_ENDRUN ? in pci_oxsemi_tornado_init()
1048 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1066 * unsigned 16-bit integer.
1080 * divisor required would be out of its unsigned 16-bit integer range.
1083 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1128 unsigned int sclk = port->uartclk * 2; in pci_oxsemi_tornado_get_divisor()
1138 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { in pci_oxsemi_tornado_get_divisor()
1139 unsigned int cust_div = port->custom_divisor; in pci_oxsemi_tornado_get_divisor()
1160 srem = spre - srem; in pci_oxsemi_tornado_get_divisor()
1223 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1231 up->mcr |= UART_MCR_CLKSEL; in pci_oxsemi_tornado_set_mctrl()
1243 struct pci_dev *dev = priv->dev; in pci_oxsemi_tornado_setup()
1246 up->port.flags |= UPF_FULL_PROBE; in pci_oxsemi_tornado_setup()
1247 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; in pci_oxsemi_tornado_setup()
1248 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; in pci_oxsemi_tornado_setup()
1249 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; in pci_oxsemi_tornado_setup()
1259 port->bugs |= UART_BUG_PARITY; in pci_asix_setup()
1304 unsigned long base = port->port.iobase; in pci_quatech_rqopr()
1316 unsigned long base = port->port.iobase; in pci_quatech_wqopr()
1328 unsigned long base = port->port.iobase; in pci_quatech_rqmcr()
1344 unsigned long base = port->port.iobase; in pci_quatech_wqmcr()
1358 unsigned long base = port->port.iobase; in pci_quatech_has_qmcr()
1382 return -EINVAL; in pci_quatech_test()
1386 return -EINVAL; in pci_quatech_test()
1390 return -EINVAL; in pci_quatech_test()
1394 return -EINVAL; in pci_quatech_test()
1466 amcc = match->driver_data; in pci_quatech_init()
1468 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); in pci_quatech_init()
1489 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); in pci_quatech_setup()
1491 port->port.uartclk = pci_quatech_clock(port); in pci_quatech_setup()
1494 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); in pci_quatech_setup()
1502 unsigned int bar, offset = board->first_offset, maxnr; in pci_default_setup()
1504 bar = FL_GET_BASE(board->flags); in pci_default_setup()
1505 if (board->flags & FL_BASE_BARS) in pci_default_setup()
1508 offset += idx * board->uart_offset; in pci_default_setup()
1510 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> in pci_default_setup()
1511 (board->reg_shift + 3); in pci_default_setup()
1513 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) in pci_default_setup()
1516 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_default_setup()
1526 ret = setup_port(priv, port, idx, 0, board->reg_shift); in ce4100_serial_setup()
1527 port->port.iotype = UPIO_MEM32; in ce4100_serial_setup()
1528 port->port.type = PORT_XSCALE; in ce4100_serial_setup()
1529 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); in ce4100_serial_setup()
1530 port->port.regshift = 2; in ce4100_serial_setup()
1550 port->port.type = PORT_BRCM_TRUMANAGE; in pci_brcm_trumanage_setup()
1551 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); in pci_brcm_trumanage_setup()
1564 struct pci_dev *pci_dev = to_pci_dev(port->dev); in pci_fintek_rs485_config()
1566 u8 *index = (u8 *) port->private_data; in pci_fintek_rs485_config()
1570 if (rs485->flags & SER_RS485_ENABLED) { in pci_fintek_rs485_config()
1574 if (rs485->flags & SER_RS485_RTS_ON_SEND) { in pci_fintek_rs485_config()
1600 struct pci_dev *pdev = priv->dev; in pci_fintek_setup()
1612 port->port.iotype = UPIO_PORT; in pci_fintek_setup()
1613 port->port.iobase = iobase; in pci_fintek_setup()
1614 port->port.rs485_config = pci_fintek_rs485_config; in pci_fintek_setup()
1615 port->port.rs485_supported = pci_fintek_rs485_supported; in pci_fintek_setup()
1617 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); in pci_fintek_setup()
1619 return -ENOMEM; in pci_fintek_setup()
1623 port->port.private_data = data; in pci_fintek_setup()
1639 return -ENODEV; in pci_fintek_init()
1641 switch (dev->device) { in pci_fintek_init()
1644 max_port = dev->device & 0xff; in pci_fintek_init()
1650 return -EINVAL; in pci_fintek_init()
1668 /* Select 128-byte FIFO and 8x FIFO threshold */ in pci_fintek_init()
1679 pci_write_config_byte(dev, config_base + 0x06, dev->irq); in pci_fintek_init()
1694 struct f815xxa_data *data = p->private_data; in f815xxa_mem_serial_out()
1697 spin_lock_irqsave(&data->lock, flags); in f815xxa_mem_serial_out()
1698 writeb(value, p->membase + offset); in f815xxa_mem_serial_out()
1699 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ in f815xxa_mem_serial_out()
1700 spin_unlock_irqrestore(&data->lock, flags); in f815xxa_mem_serial_out()
1707 struct pci_dev *pdev = priv->dev; in pci_fintek_f815xxa_setup()
1710 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); in pci_fintek_f815xxa_setup()
1712 return -ENOMEM; in pci_fintek_f815xxa_setup()
1714 data->idx = idx; in pci_fintek_f815xxa_setup()
1715 spin_lock_init(&data->lock); in pci_fintek_f815xxa_setup()
1717 port->port.private_data = data; in pci_fintek_f815xxa_setup()
1718 port->port.iotype = UPIO_MEM; in pci_fintek_f815xxa_setup()
1719 port->port.flags |= UPF_IOREMAP; in pci_fintek_f815xxa_setup()
1720 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; in pci_fintek_f815xxa_setup()
1721 port->port.serial_out = f815xxa_mem_serial_out; in pci_fintek_f815xxa_setup()
1732 return -ENODEV; in pci_fintek_f815xxa_init()
1734 switch (dev->device) { in pci_fintek_f815xxa_init()
1737 max_port = dev->device & 0xff; in pci_fintek_f815xxa_init()
1743 return -EINVAL; in pci_fintek_f815xxa_init()
1753 /* Select 128-byte FIFO and 8x FIFO threshold */ in pci_fintek_f815xxa_init()
1767 port->port.quirks |= UPQ_NO_TXEN_TEST; in skip_tx_en_setup()
1768 pci_dbg(priv->dev, in skip_tx_en_setup()
1770 priv->dev->vendor, priv->dev->device, in skip_tx_en_setup()
1771 priv->dev->subsystem_vendor, priv->dev->subsystem_device); in skip_tx_en_setup()
1799 * that instead. up->ier should be the same value as what is in kt_serial_in()
1802 val = inb(p->iobase + offset); in kt_serial_in()
1805 val = up->ier; in kt_serial_in()
1814 port->port.flags |= UPF_BUG_THRE; in kt_serial_setup()
1815 port->port.serial_in = kt_serial_in; in kt_serial_setup()
1816 port->port.handle_break = kt_handle_break; in kt_serial_setup()
1823 return -ENODEV; in pci_eg20t_init()
1834 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch353_setup()
1835 port->port.type = PORT_16550A; in pci_wch_ch353_setup()
1844 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch355_setup()
1845 port->port.type = PORT_16550A; in pci_wch_ch355_setup()
1854 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch38x_setup()
1855 port->port.type = PORT_16850; in pci_wch_ch38x_setup()
1869 switch (dev->device) { in pci_wch_ch38x_init()
1874 return -EINVAL; in pci_wch_ch38x_init()
1900 port->port.flags |= UPF_FIXED_TYPE; in pci_sunix_setup()
1901 port->port.type = PORT_SUNIX; in pci_sunix_setup()
1905 offset = idx * board->uart_offset; in pci_sunix_setup()
1908 idx -= 4; in pci_sunix_setup()
1910 offset = idx * 64 + offset * board->uart_offset; in pci_sunix_setup()
1921 unsigned int bar = FL_GET_BASE(board->flags); in pci_moxa_setup()
1924 if (board->num_ports == 4 && idx == 3) in pci_moxa_setup()
1925 offset = 7 * board->uart_offset; in pci_moxa_setup()
1927 offset = idx * board->uart_offset; in pci_moxa_setup()
1999 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2013 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2023 * AFAVLAB cards - these may be called via parport_serial
2293 * SBS Technologies, Inc., PMC-OCTALPRO 232
2305 * SBS Technologies, Inc., PMC-OCTALPRO 422
2317 * SBS Technologies, Inc., P-Octal 232
2329 * SBS Technologies, Inc., P-Octal 422
2341 * SIIG cards - these may be called via parport_serial
2409 * Netmos cards - these may be called via parport_serial
2530 * Cronyx Omega PCI (PLX-chip based)
2722 if (quirk_id_matches(quirk->vendor, dev->vendor) && in find_quirk()
2723 quirk_id_matches(quirk->device, dev->device) && in find_quirk()
2724 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && in find_quirk()
2725 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) in find_quirk()
2844 * Board-specific versions.
2898 * uart_offset - the space between channels
2899 * reg_shift - describes how the UART registers are mapped
2901 * For example IER register on SBS, Inc. PMC-OctPro is located at
3333 * Entries following this are board-specific.
3337 * Panacom - IOMEM
3361 /* I think this entry is broken - the first_offset looks wrong --rmk */
3413 * Max 256 ports.
3433 * Computone - uses IOMEM.
3467 * PA Semi PWRficient PA6T-1682M on-chip UART
3506 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3695 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3696 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3698 /* multi-io cards handled by parport_serial */
3747 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && in serial_pci_is_class_communication()
3748 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && in serial_pci_is_class_communication()
3749 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || in serial_pci_is_class_communication()
3750 (dev->class & 0xff) > 6) in serial_pci_is_class_communication()
3751 return -ENODEV; in serial_pci_is_class_communication()
3759 * serial specs. Returns 0 on success, -ENODEV on failure.
3764 int num_iomem, num_port, first_port = -1, i; in serial_pci_guess_board()
3774 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) in serial_pci_guess_board()
3775 return -ENODEV; in serial_pci_guess_board()
3781 if (first_port == -1) in serial_pci_guess_board()
3794 board->flags = first_port; in serial_pci_guess_board()
3795 board->num_ports = pci_resource_len(dev, first_port) / 8; in serial_pci_guess_board()
3804 first_port = -1; in serial_pci_guess_board()
3809 (first_port == -1 || (first_port + num_port) == i)) { in serial_pci_guess_board()
3811 if (first_port == -1) in serial_pci_guess_board()
3817 board->flags = first_port | FL_BASE_BARS; in serial_pci_guess_board()
3818 board->num_ports = num_port; in serial_pci_guess_board()
3822 return -ENODEV; in serial_pci_guess_board()
3830 board->num_ports == guessed->num_ports && in serial_pci_matches()
3831 board->base_baud == guessed->base_baud && in serial_pci_matches()
3832 board->uart_offset == guessed->uart_offset && in serial_pci_matches()
3833 board->reg_shift == guessed->reg_shift && in serial_pci_matches()
3834 board->first_offset == guessed->first_offset; in serial_pci_matches()
3845 nr_ports = board->num_ports; in pciserial_init_ports()
3853 * Run the new-style initialization function. in pciserial_init_ports()
3855 * <0 - error in pciserial_init_ports()
3856 * 0 - use board->num_ports in pciserial_init_ports()
3857 * >0 - number of ports in pciserial_init_ports()
3859 if (quirk->init) { in pciserial_init_ports()
3860 rc = quirk->init(dev); in pciserial_init_ports()
3871 priv = ERR_PTR(-ENOMEM); in pciserial_init_ports()
3875 priv->dev = dev; in pciserial_init_ports()
3876 priv->quirk = quirk; in pciserial_init_ports()
3880 uart.port.uartclk = board->base_baud * 16; in pciserial_init_ports()
3882 if (board->flags & FL_NOIRQ) { in pciserial_init_ports()
3886 pci_dbg(dev, "Using MSI(-X) interrupts\n"); in pciserial_init_ports()
3903 uart.port.dev = &dev->dev; in pciserial_init_ports()
3906 if (quirk->setup(priv, board, &uart, i)) in pciserial_init_ports()
3912 priv->line[i] = serial8250_register_8250_port(&uart); in pciserial_init_ports()
3913 if (priv->line[i] < 0) { in pciserial_init_ports()
3917 uart.port.iotype, priv->line[i]); in pciserial_init_ports()
3921 priv->nr = i; in pciserial_init_ports()
3922 priv->board = board; in pciserial_init_ports()
3926 if (quirk->exit) in pciserial_init_ports()
3927 quirk->exit(dev); in pciserial_init_ports()
3938 for (i = 0; i < priv->nr; i++) in pciserial_detach_ports()
3939 serial8250_unregister_port(priv->line[i]); in pciserial_detach_ports()
3944 quirk = find_quirk(priv->dev); in pciserial_detach_ports()
3945 if (quirk->exit) in pciserial_detach_ports()
3946 quirk->exit(priv->dev); in pciserial_detach_ports()
3960 for (i = 0; i < priv->nr; i++) in pciserial_suspend_ports()
3961 if (priv->line[i] >= 0) in pciserial_suspend_ports()
3962 serial8250_suspend_port(priv->line[i]); in pciserial_suspend_ports()
3967 if (priv->quirk->exit) in pciserial_suspend_ports()
3968 priv->quirk->exit(priv->dev); in pciserial_suspend_ports()
3979 if (priv->quirk->init) in pciserial_resume_ports()
3980 priv->quirk->init(priv->dev); in pciserial_resume_ports()
3982 for (i = 0; i < priv->nr; i++) in pciserial_resume_ports()
3983 if (priv->line[i] >= 0) in pciserial_resume_ports()
3984 serial8250_resume_port(priv->line[i]); in pciserial_resume_ports()
4003 if (quirk->probe) { in pciserial_init_one()
4004 rc = quirk->probe(dev); in pciserial_init_one()
4009 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { in pciserial_init_one()
4010 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); in pciserial_init_one()
4011 return -EINVAL; in pciserial_init_one()
4014 board = &pci_boards[ent->driver_data]; in pciserial_init_one()
4018 if (exclude->driver_data) in pciserial_init_one()
4020 (const char *)exclude->driver_data); in pciserial_init_one()
4021 return -ENODEV; in pciserial_init_one()
4029 if (ent->driver_data == pbn_default) { in pciserial_init_one()
4092 * The device may have been disabled. Re-enable it. in pciserial_resume_one()
4097 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); in pciserial_resume_one()
4231 /* Unknown card - subdevice 0x1584 */
4236 /* Unknown card - subdevice 0x1588 */
4532 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4535 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4538 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4541 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4546 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4560 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4577 * Digitan DS560-558, from jimd@esoft.com
4853 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4860 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4887 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4949 * IntaShield IS-200
4955 * IntaShield IS-400
4962 * Brainboxes UC-101
4969 * Brainboxes UC-235/246
4976 * Brainboxes UC-257
4983 * Brainboxes UC-260/271/701/756
4994 * Brainboxes UC-268
5001 * Brainboxes UC-275/279
5008 * Brainboxes UC-302
5015 * Brainboxes UC-310
5022 * Brainboxes UC-313
5029 * Brainboxes UC-320/324
5036 * Brainboxes UC-346
5043 * Brainboxes UC-357
5054 * Brainboxes UC-368
5061 * Brainboxes UC-420/431
5068 * Brainboxes PX-101
5079 * Brainboxes PX-235/246
5090 * Brainboxes PX-203/PX-257
5101 * Brainboxes PX-260/PX-701
5108 * Brainboxes PX-310
5115 * Brainboxes PX-313
5122 * Brainboxes PX-320/324/PX-376/PX-387
5129 * Brainboxes PX-335/346
5136 * Brainboxes PX-368
5143 * Brainboxes PX-420
5154 * Brainboxes PX-803
5165 * Brainboxes PX-846
5177 * Perle PCI-RAS cards
5299 * PA Semi PA6T-1682M on-chip UART
5422 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5614 * AgeStar as-prs2-009
5666 /* MKS Tenta SCOM-080x serial cards */
5731 new = pciserial_init_ports(dev, priv->board); in serial8250_io_resume()