1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6  * Ingenic SoC UART support
47 	return readl(port->membase + (offset << 2));  in early_in()
52 	writel(value, port->membase + (offset << 2));  in early_out()
69 	uart_console_write(&early_device->port, s, count,  in ingenic_early_console_write()
83 	prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);  in ingenic_early_console_setup_clock()
87 	dev->port.uartclk = be32_to_cpup(prop);  in ingenic_early_console_setup_clock()
93 	struct uart_port *port = &dev->port;  in ingenic_early_console_setup()
97 	if (!dev->port.membase)  in ingenic_early_console_setup()
98 		return -ENODEV;  in ingenic_early_console_setup()
108 	if (dev->baud)  in ingenic_early_console_setup()
109 		baud = dev->baud;  in ingenic_early_console_setup()
110 	divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);  in ingenic_early_console_setup()
127 	dev->con->write = ingenic_early_console_write;  in ingenic_early_console_setup()
132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
153 		/* UART module enable */  in ingenic_uart_serial_out()
170 		ier = p->serial_in(p, UART_IER);  in ingenic_uart_serial_out()
182 	writeb(value, p->membase + (offset << p->regshift));  in ingenic_uart_serial_out()
189 	value = readb(p->membase + (offset << p->regshift));  in ingenic_uart_serial_in()
191 	/* Hide non-16550 compliant bits from higher levels */  in ingenic_uart_serial_in()
209 	struct uart_8250_port uart = {};  in ingenic_uart_probe()  local
215 	cdata = of_device_get_match_data(&pdev->dev);  in ingenic_uart_probe()
217 		dev_err(&pdev->dev, "Error: No device match found\n");  in ingenic_uart_probe()
218 		return -ENODEV;  in ingenic_uart_probe()
227 		dev_err(&pdev->dev, "no registers defined\n");  in ingenic_uart_probe()
228 		return -EINVAL;  in ingenic_uart_probe()
231 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);  in ingenic_uart_probe()
233 		return -ENOMEM;  in ingenic_uart_probe()
235 	spin_lock_init(&uart.port.lock);  in ingenic_uart_probe()
236 	uart.port.type = PORT_16550A;  in ingenic_uart_probe()
237 	uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;  in ingenic_uart_probe()
238 	uart.port.iotype = UPIO_MEM;  in ingenic_uart_probe()
239 	uart.port.mapbase = regs->start;  in ingenic_uart_probe()
240 	uart.port.regshift = 2;  in ingenic_uart_probe()
241 	uart.port.serial_out = ingenic_uart_serial_out;  in ingenic_uart_probe()
242 	uart.port.serial_in = ingenic_uart_serial_in;  in ingenic_uart_probe()
243 	uart.port.irq = irq;  in ingenic_uart_probe()
244 	uart.port.dev = &pdev->dev;  in ingenic_uart_probe()
245 	uart.port.fifosize = cdata->fifosize;  in ingenic_uart_probe()
246 	uart.tx_loadsz = cdata->tx_loadsz;  in ingenic_uart_probe()
247 	uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;  in ingenic_uart_probe()
250 	line = of_alias_get_id(pdev->dev.of_node, "serial");  in ingenic_uart_probe()
252 		uart.port.line = line;  in ingenic_uart_probe()
254 	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,  in ingenic_uart_probe()
256 	if (!uart.port.membase)  in ingenic_uart_probe()
257 		return -ENOMEM;  in ingenic_uart_probe()
259 	data->clk_module = devm_clk_get(&pdev->dev, "module");  in ingenic_uart_probe()
260 	if (IS_ERR(data->clk_module))  in ingenic_uart_probe()
261 		return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),  in ingenic_uart_probe()
264 	data->clk_baud = devm_clk_get(&pdev->dev, "baud");  in ingenic_uart_probe()
265 	if (IS_ERR(data->clk_baud))  in ingenic_uart_probe()
266 		return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),  in ingenic_uart_probe()
269 	err = clk_prepare_enable(data->clk_module);  in ingenic_uart_probe()
271 		dev_err(&pdev->dev, "could not enable module clock: %d\n", err);  in ingenic_uart_probe()
275 	err = clk_prepare_enable(data->clk_baud);  in ingenic_uart_probe()
277 		dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);  in ingenic_uart_probe()
280 	uart.port.uartclk = clk_get_rate(data->clk_baud);  in ingenic_uart_probe()
282 	data->line = serial8250_register_8250_port(&uart);  in ingenic_uart_probe()
283 	if (data->line < 0) {  in ingenic_uart_probe()
284 		err = data->line;  in ingenic_uart_probe()
292 	clk_disable_unprepare(data->clk_baud);  in ingenic_uart_probe()
294 	clk_disable_unprepare(data->clk_module);  in ingenic_uart_probe()
303 	serial8250_unregister_port(data->line);  in ingenic_uart_remove()
304 	clk_disable_unprepare(data->clk_module);  in ingenic_uart_remove()
305 	clk_disable_unprepare(data->clk_baud);  in ingenic_uart_remove()
330 	{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
331 	{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
332 	{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
333 	{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
334 	{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
335 	{ .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
342 		.name		= "ingenic-uart",
353 MODULE_DESCRIPTION("Ingenic SoC UART driver");