Lines Matching +full:ri +full:- +full:override
1 // SPDX-License-Identifier: GPL-2.0+
72 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
74 /* Override any modem control signals if needed */ in dw8250_modify_msr()
76 value |= d->msr_mask_on; in dw8250_modify_msr()
77 value &= ~d->msr_mask_off; in dw8250_modify_msr()
95 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
96 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
101 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
106 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
110 while (tries--) { in dw8250_check_lcr()
111 unsigned int lcr = p->serial_in(p, UART_LCR); in dw8250_check_lcr()
119 if (p->type == PORT_OCTEON) in dw8250_check_lcr()
123 if (p->iotype == UPIO_MEM32) in dw8250_check_lcr()
125 else if (p->iotype == UPIO_MEM32BE) in dw8250_check_lcr()
131 * FIXME: this deadlocks if port->lock is already held in dw8250_check_lcr()
132 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); in dw8250_check_lcr()
141 unsigned int delay_threshold = tries - 1000; in dw8250_tx_wait_empty()
144 while (tries--) { in dw8250_tx_wait_empty()
145 lsr = readb (p->membase + (UART_LSR << p->regshift)); in dw8250_tx_wait_empty()
146 up->lsr_saved_flags |= lsr & up->lsr_save_mask; in dw8250_tx_wait_empty()
153 * the buffer has still not emptied, allow more time for low- in dw8250_tx_wait_empty()
162 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out()
164 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out()
166 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out()
181 unsigned int value = readb(p->membase + (offset << p->regshift)); in dw8250_serial_in()
191 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); in dw8250_serial_inq()
198 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_outq()
201 __raw_writeq(value, p->membase + (offset << p->regshift)); in dw8250_serial_outq()
203 __raw_readq(p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
205 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_outq()
212 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32()
214 writel(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32()
216 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32()
222 unsigned int value = readl(p->membase + (offset << p->regshift)); in dw8250_serial_in32()
229 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32be()
231 iowrite32be(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32be()
233 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32be()
239 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); in dw8250_serial_in32be()
248 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_handle_irq()
249 unsigned int iir = p->serial_in(p, UART_IIR); in dw8250_handle_irq()
251 unsigned int quirks = d->pdata->quirks; in dw8250_handle_irq()
256 * There are ways to get Designware-based UARTs into a state where in dw8250_handle_irq()
263 * so we limit the workaround only to non-DMA mode. in dw8250_handle_irq()
265 if (!up->dma && rx_timeout) { in dw8250_handle_irq()
266 spin_lock_irqsave(&p->lock, flags); in dw8250_handle_irq()
270 (void) p->serial_in(p, UART_RX); in dw8250_handle_irq()
272 spin_unlock_irqrestore(&p->lock, flags); in dw8250_handle_irq()
276 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { in dw8250_handle_irq()
277 spin_lock_irqsave(&p->lock, flags); in dw8250_handle_irq()
279 spin_unlock_irqrestore(&p->lock, flags); in dw8250_handle_irq()
292 (void)p->serial_in(p, d->pdata->usr_reg); in dw8250_handle_irq()
306 rate = clk_get_rate(d->clk); in dw8250_clk_work_cb()
310 up = serial8250_get_port(d->data.line); in dw8250_clk_work_cb()
312 serial8250_update_uartclk(&up->port, rate); in dw8250_clk_work_cb()
325 * the clk and tty-port mutexes lock. It happens if clock rate change in dw8250_clk_notifier_cb()
327 * tty-port mutex lock and clk_set_rate() function invocation and in dw8250_clk_notifier_cb()
328 * vise-versa. Anyway if we didn't have the reference clock alteration in dw8250_clk_notifier_cb()
333 queue_work(system_unbound_wq, &d->clk_work); in dw8250_clk_notifier_cb()
344 pm_runtime_get_sync(port->dev); in dw8250_do_pm()
349 pm_runtime_put_sync_suspend(port->dev); in dw8250_do_pm()
356 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_set_termios()
360 clk_disable_unprepare(d->clk); in dw8250_set_termios()
361 rate = clk_round_rate(d->clk, newrate); in dw8250_set_termios()
364 * Note that any clock-notifer worker will block in in dw8250_set_termios()
367 ret = clk_set_rate(d->clk, newrate); in dw8250_set_termios()
369 p->uartclk = rate; in dw8250_set_termios()
371 clk_prepare_enable(d->clk); in dw8250_set_termios()
379 unsigned int mcr = p->serial_in(p, UART_MCR); in dw8250_set_ldisc()
381 if (up->capabilities & UART_CAP_IRDA) { in dw8250_set_ldisc()
382 if (termios->c_line == N_IRDA) in dw8250_set_ldisc()
387 p->serial_out(p, UART_MCR, mcr); in dw8250_set_ldisc()
407 return param == chan->device->dev; in dw8250_idma_filter()
422 struct uart_port *up = &p->port; in dw8250_prepare_tx_dma()
423 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_tx_dma()
427 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | in dw8250_prepare_tx_dma()
428 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | in dw8250_prepare_tx_dma()
435 struct uart_port *up = &p->port; in dw8250_prepare_rx_dma()
436 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_rx_dma()
440 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | in dw8250_prepare_rx_dma()
441 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | in dw8250_prepare_rx_dma()
448 struct device_node *np = p->dev->of_node; in dw8250_quirks()
451 unsigned int quirks = data->pdata->quirks; in dw8250_quirks()
457 p->line = id; in dw8250_quirks()
460 p->serial_in = dw8250_serial_inq; in dw8250_quirks()
461 p->serial_out = dw8250_serial_outq; in dw8250_quirks()
462 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; in dw8250_quirks()
463 p->type = PORT_OCTEON; in dw8250_quirks()
464 data->skip_autocfg = true; in dw8250_quirks()
469 p->iotype = UPIO_MEM32BE; in dw8250_quirks()
470 p->serial_in = dw8250_serial_in32be; in dw8250_quirks()
471 p->serial_out = dw8250_serial_out32be; in dw8250_quirks()
475 p->serial_out = dw8250_serial_out38x; in dw8250_quirks()
477 p->set_termios = dw8250_do_set_termios; in dw8250_quirks()
479 data->data.dma.txconf.device_fc = 1; in dw8250_quirks()
480 data->data.dma.rxconf.device_fc = 1; in dw8250_quirks()
481 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; in dw8250_quirks()
482 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; in dw8250_quirks()
485 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { in dw8250_quirks()
486 p->iotype = UPIO_MEM32; in dw8250_quirks()
487 p->regshift = 2; in dw8250_quirks()
488 p->serial_in = dw8250_serial_in32; in dw8250_quirks()
489 data->uart_16550_compatible = true; in dw8250_quirks()
492 /* Platforms with iDMA 64-bit */ in dw8250_quirks()
493 if (platform_get_resource_byname(to_platform_device(p->dev), in dw8250_quirks()
495 data->data.dma.rx_param = p->dev->parent; in dw8250_quirks()
496 data->data.dma.tx_param = p->dev->parent; in dw8250_quirks()
497 data->data.dma.fn = dw8250_idma_filter; in dw8250_quirks()
514 struct uart_port *p = &up->port; in dw8250_probe()
515 struct device *dev = &pdev->dev; in dw8250_probe()
524 return dev_err_probe(dev, -EINVAL, "no registers defined\n"); in dw8250_probe()
530 spin_lock_init(&p->lock); in dw8250_probe()
531 p->mapbase = regs->start; in dw8250_probe()
532 p->irq = irq; in dw8250_probe()
533 p->handle_irq = dw8250_handle_irq; in dw8250_probe()
534 p->pm = dw8250_do_pm; in dw8250_probe()
535 p->type = PORT_8250; in dw8250_probe()
536 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; in dw8250_probe()
537 p->dev = dev; in dw8250_probe()
538 p->iotype = UPIO_MEM; in dw8250_probe()
539 p->serial_in = dw8250_serial_in; in dw8250_probe()
540 p->serial_out = dw8250_serial_out; in dw8250_probe()
541 p->set_ldisc = dw8250_set_ldisc; in dw8250_probe()
542 p->set_termios = dw8250_set_termios; in dw8250_probe()
544 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); in dw8250_probe()
545 if (!p->membase) in dw8250_probe()
546 return -ENOMEM; in dw8250_probe()
550 return -ENOMEM; in dw8250_probe()
552 data->data.dma.fn = dw8250_fallback_dma_filter; in dw8250_probe()
553 data->pdata = device_get_match_data(p->dev); in dw8250_probe()
554 p->private_data = &data->data; in dw8250_probe()
556 data->uart_16550_compatible = device_property_read_bool(dev, in dw8250_probe()
557 "snps,uart-16550-compatible"); in dw8250_probe()
559 err = device_property_read_u32(dev, "reg-shift", &val); in dw8250_probe()
561 p->regshift = val; in dw8250_probe()
563 err = device_property_read_u32(dev, "reg-io-width", &val); in dw8250_probe()
565 p->iotype = UPIO_MEM32; in dw8250_probe()
566 p->serial_in = dw8250_serial_in32; in dw8250_probe()
567 p->serial_out = dw8250_serial_out32; in dw8250_probe()
570 if (device_property_read_bool(dev, "dcd-override")) { in dw8250_probe()
572 data->msr_mask_on |= UART_MSR_DCD; in dw8250_probe()
573 data->msr_mask_off |= UART_MSR_DDCD; in dw8250_probe()
576 if (device_property_read_bool(dev, "dsr-override")) { in dw8250_probe()
578 data->msr_mask_on |= UART_MSR_DSR; in dw8250_probe()
579 data->msr_mask_off |= UART_MSR_DDSR; in dw8250_probe()
582 if (device_property_read_bool(dev, "cts-override")) { in dw8250_probe()
584 data->msr_mask_on |= UART_MSR_CTS; in dw8250_probe()
585 data->msr_mask_off |= UART_MSR_DCTS; in dw8250_probe()
588 if (device_property_read_bool(dev, "ri-override")) { in dw8250_probe()
590 data->msr_mask_off |= UART_MSR_RI; in dw8250_probe()
591 data->msr_mask_off |= UART_MSR_TERI; in dw8250_probe()
595 device_property_read_u32(dev, "clock-frequency", &p->uartclk); in dw8250_probe()
598 data->clk = devm_clk_get_optional(dev, "baudclk"); in dw8250_probe()
599 if (data->clk == NULL) in dw8250_probe()
600 data->clk = devm_clk_get_optional(dev, NULL); in dw8250_probe()
601 if (IS_ERR(data->clk)) in dw8250_probe()
602 return PTR_ERR(data->clk); in dw8250_probe()
604 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); in dw8250_probe()
605 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; in dw8250_probe()
607 err = clk_prepare_enable(data->clk); in dw8250_probe()
611 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk); in dw8250_probe()
615 if (data->clk) in dw8250_probe()
616 p->uartclk = clk_get_rate(data->clk); in dw8250_probe()
619 if (!p->uartclk) in dw8250_probe()
620 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); in dw8250_probe()
622 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); in dw8250_probe()
623 if (IS_ERR(data->pclk)) in dw8250_probe()
624 return PTR_ERR(data->pclk); in dw8250_probe()
626 err = clk_prepare_enable(data->pclk); in dw8250_probe()
630 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk); in dw8250_probe()
634 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); in dw8250_probe()
635 if (IS_ERR(data->rst)) in dw8250_probe()
636 return PTR_ERR(data->rst); in dw8250_probe()
638 reset_control_deassert(data->rst); in dw8250_probe()
640 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); in dw8250_probe()
647 if (data->uart_16550_compatible) in dw8250_probe()
648 p->handle_irq = NULL; in dw8250_probe()
650 if (!data->skip_autocfg) in dw8250_probe()
654 if (p->fifosize) { in dw8250_probe()
655 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; in dw8250_probe()
656 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; in dw8250_probe()
657 up->dma = &data->data.dma; in dw8250_probe()
660 data->data.line = serial8250_register_8250_port(up); in dw8250_probe()
661 if (data->data.line < 0) in dw8250_probe()
662 return data->data.line; in dw8250_probe()
669 if (data->clk) { in dw8250_probe()
670 err = clk_notifier_register(data->clk, &data->clk_notifier); in dw8250_probe()
673 queue_work(system_unbound_wq, &data->clk_work); in dw8250_probe()
687 struct device *dev = &pdev->dev; in dw8250_remove()
691 if (data->clk) { in dw8250_remove()
692 clk_notifier_unregister(data->clk, &data->clk_notifier); in dw8250_remove()
694 flush_work(&data->clk_work); in dw8250_remove()
697 serial8250_unregister_port(data->data.line); in dw8250_remove()
709 serial8250_suspend_port(data->data.line); in dw8250_suspend()
718 serial8250_resume_port(data->data.line); in dw8250_resume()
727 clk_disable_unprepare(data->clk); in dw8250_runtime_suspend()
729 clk_disable_unprepare(data->pclk); in dw8250_runtime_suspend()
738 clk_prepare_enable(data->pclk); in dw8250_runtime_resume()
740 clk_prepare_enable(data->clk); in dw8250_runtime_resume()
776 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
777 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
778 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
779 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
780 { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
804 .name = "dw-apb-uart",
818 MODULE_ALIAS("platform:dw-apb-uart");