345 		seq_puts(s, "# hardware margining: yes\n");  in margining_caps_show()
346 		seq_puts(s, "# minimum BER level contour: ");  in margining_caps_show()
348 		seq_puts(s, "# maximum BER level contour: ");  in margining_caps_show()
351 		seq_puts(s, "# hardware margining: no\n");  in margining_caps_show()
363 		seq_puts(s, "# returns minimum between high and low voltage margins\n");  in margining_caps_show()
366 		seq_puts(s, "# returns high or low voltage margin\n");  in margining_caps_show()
369 		seq_puts(s, "# returns both high and low margins\n");  in margining_caps_show()
374 		seq_puts(s, "# time margining: yes\n");  in margining_caps_show()
380 			seq_puts(s, "# returns minimum between left and right time margins\n");  in margining_caps_show()
383 			seq_puts(s, "# returns left or right margin\n");  in margining_caps_show()
386 			seq_puts(s, "# returns both left and right margins\n");  in margining_caps_show()
395 		seq_puts(s, "# time margining: no\n");  in margining_caps_show()
459 			seq_puts(s, "[0] 1 all\n");  in margining_lanes_show()
461 			seq_puts(s, "0 [1] all\n");  in margining_lanes_show()
463 			seq_puts(s, "0 1 [all]\n");  in margining_lanes_show()
466 			seq_puts(s, "[0] 1\n");  in margining_lanes_show()
468 			seq_puts(s, "0 [1]\n");  in margining_lanes_show()
531 			seq_puts(s, "[software]");  in margining_mode_show()
533 			seq_puts(s, "software");  in margining_mode_show()
545 	seq_puts(s, "\n");  in margining_mode_show()
643 		seq_puts(s, " exceeds maximum");  in voltage_margin_show()
644 	seq_puts(s, "\n");  in voltage_margin_show()
656 		seq_puts(s, " exceeds maximum");  in time_margin_show()
657 	seq_puts(s, "\n");  in time_margin_show()
682 				seq_puts(s, "# lane 0 right time margin: ");  in margining_results_show()
686 				seq_puts(s, "# lane 0 left time margin: ");  in margining_results_show()
692 				seq_puts(s, "# lane 1 right time margin: ");  in margining_results_show()
696 				seq_puts(s, "# lane 1 left time margin: ");  in margining_results_show()
702 				seq_puts(s, "# lane 0 high voltage margin: ");  in margining_results_show()
706 				seq_puts(s, "# lane 0 low voltage margin: ");  in margining_results_show()
712 				seq_puts(s, "# lane 1 high voltage margin: ");  in margining_results_show()
716 				seq_puts(s, "# lane 1 low voltage margin: ");  in margining_results_show()
774 			seq_puts(s, "voltage [time]\n");  in margining_test_show()
776 			seq_puts(s, "[voltage] time\n");  in margining_test_show()
778 		seq_puts(s, "[voltage]\n");  in margining_test_show()
842 			seq_puts(s, "left [right]\n");  in margining_margin_show()
844 			seq_puts(s, "[left] right\n");  in margining_margin_show()
847 			seq_puts(s, "low [high]\n");  in margining_margin_show()
849 			seq_puts(s, "[low] high\n");  in margining_margin_show()
1243 	seq_puts(s, "# offset relative_offset cap_id vs_cap_id value\n");  in port_regs_show()
1347 	seq_puts(s, "# offset relative_offset cap_id vs_cap_id value\n");  in switch_regs_show()
1399 	seq_puts(s, "# offset relative_offset in_hop_id value\n");  in path_show()
1462 	seq_puts(s, "# offset relative_offset counter_id value\n");  in counters_show()