Lines Matching +full:0 +full:x160
24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
110 .pllx_hotspot_diff = 0,
131 .base = 0xc0,
133 .calib_fuse_offset = 0x098,
139 .base = 0xe0,
141 .calib_fuse_offset = 0x084,
147 .base = 0x100,
149 .calib_fuse_offset = 0x088,
155 .base = 0x120,
157 .calib_fuse_offset = 0x12c,
163 .base = 0x140,
165 .calib_fuse_offset = 0x158,
171 .base = 0x160,
173 .calib_fuse_offset = 0x15c,
179 .base = 0x180,
181 .calib_fuse_offset = 0x154,
187 .base = 0x1a0,
189 .calib_fuse_offset = 0x160,
202 .fuse_base_cp_mask = 0x3ff << 11,
204 .fuse_base_ft_mask = 0x7ff << 21,
206 .fuse_shift_ft_mask = 0x1f << 6,
208 .fuse_spare_realignment = 0,