Lines Matching +full:0 +full:x160
23 #define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28)
24 #define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27)
25 #define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26)
26 #define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25)
27 #define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
28 #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
29 #define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
30 #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff
32 #define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
33 #define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
109 .pllx_hotspot_diff = 0,
130 .base = 0xc0,
132 .calib_fuse_offset = 0x098,
138 .base = 0xe0,
140 .calib_fuse_offset = 0x084,
146 .base = 0x100,
148 .calib_fuse_offset = 0x088,
154 .base = 0x120,
156 .calib_fuse_offset = 0x12c,
162 .base = 0x140,
164 .calib_fuse_offset = 0x158,
170 .base = 0x160,
172 .calib_fuse_offset = 0x15c,
178 .base = 0x180,
180 .calib_fuse_offset = 0x154,
186 .base = 0x1a0,
188 .calib_fuse_offset = 0x160,
201 .fuse_base_cp_mask = 0x3ff,
202 .fuse_base_cp_shift = 0,
203 .fuse_base_ft_mask = 0x7ff << 10,
205 .fuse_shift_ft_mask = 0x1f << 21,
207 .fuse_spare_realignment = 0x1fc,