28 	TSHUT_MODE_CRU = 0,
35  * 0: low active, 1: high active
38 	TSHUT_LOW_ACTIVE = 0,
47 	SENSOR_CPU = 0,
57 	ADC_DECREMENT = 0,
88  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
89  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
151  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
152  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
179 #define TSADCV2_USER_CON			0x00
180 #define TSADCV2_AUTO_CON			0x04
181 #define TSADCV2_INT_EN				0x08
182 #define TSADCV2_INT_PD				0x0c
183 #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
184 #define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
185 #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
186 #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
187 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
188 #define TSADCV2_AUTO_PERIOD			0x68
189 #define TSADCV2_AUTO_PERIOD_HT			0x6c
191 #define TSADCV2_AUTO_EN				BIT(0)
204 #define TSADCV2_DATA_MASK			0xfff
205 #define TSADCV3_DATA_MASK			0x3ff
217 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
218 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
220 #define GRF_SARADC_TESTBIT			0x0e644
221 #define GRF_TSADC_TESTBIT_L			0x0e648
222 #define GRF_TSADC_TESTBIT_H			0x0e64c
224 #define PX30_GRF_SOC_CON2			0x0408
226 #define RK3568_GRF_TSADC_CON			0x0600
227 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
228 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
229 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
230 #define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
232 #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
233 #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
234 #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
235 #define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
237 #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
255 	{0, -40000},
264 	{436, 0},
294 	{0, -40000},
303 	{629, 0},
342 	{3728, 0},
368 	{0, 125000},
372 	{0, -40000},
380 	{368, 0},
410 	{0, -40000},
419 	{122, 0},
449 	{0, -40000},
458 	{470, 0},
488 	{0, -40000},
497 	{1856, 0},
534 	low = 0;  in rk_tsadcv2_temp_to_code()
640 	return 0;  in rk_tsadcv2_code_to_temp()
647  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
665 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
668 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
684  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
739 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
742 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
766 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
769 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
873 		return 0;  in rk_tsadcv2_alarm_temp()
888 	return 0;  in rk_tsadcv2_alarm_temp()
907 	return 0;  in rk_tsadcv2_tshut_temp()
928 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
952 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
976 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1025 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1048 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1073 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1098 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1123 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1207 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_alarm_irq_thread()
1307 	return 0;  in rockchip_configure_from_dt()
1338 	return 0;  in rockchip_thermal_register_sensor()
1366 	irq = platform_get_irq(pdev, 0);  in rockchip_thermal_probe()
1367 	if (irq < 0)  in rockchip_thermal_probe()
1381 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rockchip_thermal_probe()
1433 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1457 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1469 	return 0;  in rockchip_thermal_probe()
1484 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_remove()
1496 	return 0;  in rockchip_thermal_remove()
1504 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_suspend()
1514 	return 0;  in rockchip_thermal_suspend()
1538 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_resume()
1554 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_resume()
1559 	return 0;  in rockchip_thermal_resume()