716 	void __iomem *controller_base = mt->thermal_base + offset;  in mtk_thermal_init_bank()  local
724 	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);  in mtk_thermal_init_bank()
732 			controller_base + TEMP_MONCTL2);  in mtk_thermal_init_bank()
736 	       controller_base + TEMP_AHBPOLL);  in mtk_thermal_init_bank()
739 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
742 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
745 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
746 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
761 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);  in mtk_thermal_init_bank()
765 	       controller_base + TEMP_ADCMUXADDR);  in mtk_thermal_init_bank()
770 		       controller_base + TEMP_PNPMUXADDR);  in mtk_thermal_init_bank()
774 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);  in mtk_thermal_init_bank()
778 	       controller_base + TEMP_ADCENADDR);  in mtk_thermal_init_bank()
782 	       controller_base + TEMP_ADCVALIDADDR);  in mtk_thermal_init_bank()
786 	       controller_base + TEMP_ADCVOLTADDR);  in mtk_thermal_init_bank()
789 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
793 	       controller_base + TEMP_ADCVALIDMASK);  in mtk_thermal_init_bank()
796 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
800 		controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()
807 	       controller_base + TEMP_MONCTL0);  in mtk_thermal_init_bank()
811 	       controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()