Lines Matching +full:mediatek +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
15 #include <linux/nvmem-consumer.h>
22 #include <linux/thermal.h>
36 /* Thermal Controller Registers */
93 /* MT8173 thermal sensors */
168 /* MT2701 thermal sensors */
188 /* MT2712 thermal sensors */
222 /* MT8183 thermal sensors */
297 /* MT8183 thermal sensor data */
318 /* MT8173 thermal sensor data */
341 /* MT2701 thermal sensor data */
361 /* MT2712 thermal sensor data */
381 /* MT7622 thermal sensor data */
390 * The MT8173 thermal controller has four banks. Each bank can read up to
396 * The thermal core only gets the maximum temperature of all banks, so
433 * The MT2701 thermal controller has one bank, which can read up to
437 * The thermal core only gets the maximum temperature of this one bank,
464 * The MT2712 thermal controller has one bank, which can read up to
468 * The thermal core only gets the maximum temperature of this one bank,
520 * The MT8183 thermal controller has one bank for the current SW framework.
522 * There are two thermal controller to control the six sensor.
524 * The thermal core only gets the maximum temperature of all sensor, so
553 * raw_to_mcelsius - convert a raw ADC value to mcelsius
554 * @mt: The thermal controller
568 tmp /= mt->conf->cali_val + mt->o_slope; in raw_to_mcelsius_v1()
569 tmp /= 10000 + mt->adc_ge; in raw_to_mcelsius_v1()
570 tmp *= raw - mt->vts[sensno] - 3350; in raw_to_mcelsius_v1()
573 return mt->degc_cali * 500 - tmp; in raw_to_mcelsius_v1()
589 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); in raw_to_mcelsius_v2()
590 g_oe = mt->adc_oe - 512; in raw_to_mcelsius_v2()
591 format_1 = mt->vts[VTS2] + 3105 - g_oe; in raw_to_mcelsius_v2()
592 format_2 = (mt->degc_cali * 10) >> 1; in raw_to_mcelsius_v2()
595 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; in raw_to_mcelsius_v2()
598 if (mt->o_slope_sign == 0) in raw_to_mcelsius_v2()
599 tmp = tmp / (165 - mt->o_slope); in raw_to_mcelsius_v2()
601 tmp = tmp / (165 + mt->o_slope); in raw_to_mcelsius_v2()
603 return (format_2 - tmp) * 100; in raw_to_mcelsius_v2()
607 * mtk_thermal_get_bank - get bank
615 struct mtk_thermal *mt = bank->mt; in mtk_thermal_get_bank()
618 if (mt->conf->need_switch_bank) { in mtk_thermal_get_bank()
619 mutex_lock(&mt->lock); in mtk_thermal_get_bank()
621 val = readl(mt->thermal_base + PTPCORESEL); in mtk_thermal_get_bank()
623 val |= bank->id; in mtk_thermal_get_bank()
624 writel(val, mt->thermal_base + PTPCORESEL); in mtk_thermal_get_bank()
629 * mtk_thermal_put_bank - release bank
636 struct mtk_thermal *mt = bank->mt; in mtk_thermal_put_bank()
638 if (mt->conf->need_switch_bank) in mtk_thermal_put_bank()
639 mutex_unlock(&mt->lock); in mtk_thermal_put_bank()
643 * mtk_thermal_bank_temperature - get the temperature of a bank
651 struct mtk_thermal *mt = bank->mt; in mtk_thermal_bank_temperature()
652 const struct mtk_thermal_data *conf = mt->conf; in mtk_thermal_bank_temperature()
656 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { in mtk_thermal_bank_temperature()
657 raw = readl(mt->thermal_base + conf->msr[i]); in mtk_thermal_bank_temperature()
659 if (mt->conf->version == MTK_THERMAL_V1) { in mtk_thermal_bank_temperature()
661 mt, conf->bank_data[bank->id].sensors[i], raw); in mtk_thermal_bank_temperature()
664 mt, conf->bank_data[bank->id].sensors[i], raw); in mtk_thermal_bank_temperature()
684 struct mtk_thermal *mt = tz->devdata; in mtk_read_temp()
688 for (i = 0; i < mt->conf->num_banks; i++) { in mtk_read_temp()
689 struct mtk_thermal_bank *bank = &mt->banks[i]; in mtk_read_temp()
711 struct mtk_thermal_bank *bank = &mt->banks[num]; in mtk_thermal_init_bank()
712 const struct mtk_thermal_data *conf = mt->conf; in mtk_thermal_init_bank()
715 int offset = mt->conf->controller_offset[ctrl_id]; in mtk_thermal_init_bank()
716 void __iomem *controller_base = mt->thermal_base + offset; in mtk_thermal_init_bank()
718 bank->id = num; in mtk_thermal_init_bank()
719 bank->mt = mt; in mtk_thermal_init_bank()
749 * The MT8173 thermal controller does not have its own ADC. Instead it in mtk_thermal_init_bank()
750 * uses AHB bus accesses to control the AUXADC. To do this the thermal in mtk_thermal_init_bank()
753 * Also the thermal controller controls a mux in the APMIXEDSYS register in mtk_thermal_init_bank()
761 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); in mtk_thermal_init_bank()
767 if (mt->conf->version == MTK_THERMAL_V1) { in mtk_thermal_init_bank()
774 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); in mtk_thermal_init_bank()
781 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), in mtk_thermal_init_bank()
785 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), in mtk_thermal_init_bank()
802 for (i = 0; i < conf->bank_data[num].num_sensors; i++) in mtk_thermal_init_bank()
803 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], in mtk_thermal_init_bank()
804 mt->thermal_base + conf->adcpnp[i]); in mtk_thermal_init_bank()
806 writel((1 << conf->bank_data[num].num_sensors) - 1, in mtk_thermal_init_bank()
833 return -EINVAL; in mtk_thermal_extract_efuse_v1()
835 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); in mtk_thermal_extract_efuse_v1()
837 for (i = 0; i < mt->conf->num_sensors; i++) { in mtk_thermal_extract_efuse_v1()
838 switch (mt->conf->vts_index[i]) { in mtk_thermal_extract_efuse_v1()
840 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
843 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
846 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); in mtk_thermal_extract_efuse_v1()
849 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); in mtk_thermal_extract_efuse_v1()
852 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); in mtk_thermal_extract_efuse_v1()
855 mt->vts[VTSABB] = in mtk_thermal_extract_efuse_v1()
863 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
866 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
868 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
876 return -EINVAL; in mtk_thermal_extract_efuse_v2()
878 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
879 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
880 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
881 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
882 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
883 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
884 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
885 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
899 mt->adc_ge = 512; in mtk_thermal_get_calibration_data()
900 for (i = 0; i < mt->conf->num_sensors; i++) in mtk_thermal_get_calibration_data()
901 mt->vts[i] = 260; in mtk_thermal_get_calibration_data()
902 mt->degc_cali = 40; in mtk_thermal_get_calibration_data()
903 mt->o_slope = 0; in mtk_thermal_get_calibration_data()
905 cell = nvmem_cell_get(dev, "calibration-data"); in mtk_thermal_get_calibration_data()
907 if (PTR_ERR(cell) == -EPROBE_DEFER) in mtk_thermal_get_calibration_data()
921 ret = -EINVAL; in mtk_thermal_get_calibration_data()
925 if (mt->conf->version == MTK_THERMAL_V1) in mtk_thermal_get_calibration_data()
943 .compatible = "mediatek,mt8173-thermal",
947 .compatible = "mediatek,mt2701-thermal",
951 .compatible = "mediatek,mt2712-thermal",
955 .compatible = "mediatek,mt7622-thermal",
959 .compatible = "mediatek,mt8183-thermal",
983 writel(0x1, mt->thermal_base + TEMP_MONCTL0); in mtk_thermal_release_periodic_ts()
984 tmp = readl(mt->thermal_base + TEMP_MSRCTL1); in mtk_thermal_release_periodic_ts()
985 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); in mtk_thermal_release_periodic_ts()
991 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; in mtk_thermal_probe()
998 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); in mtk_thermal_probe()
1000 return -ENOMEM; in mtk_thermal_probe()
1002 mt->conf = of_device_get_match_data(&pdev->dev); in mtk_thermal_probe()
1004 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); in mtk_thermal_probe()
1005 if (IS_ERR(mt->clk_peri_therm)) in mtk_thermal_probe()
1006 return PTR_ERR(mt->clk_peri_therm); in mtk_thermal_probe()
1008 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); in mtk_thermal_probe()
1009 if (IS_ERR(mt->clk_auxadc)) in mtk_thermal_probe()
1010 return PTR_ERR(mt->clk_auxadc); in mtk_thermal_probe()
1013 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); in mtk_thermal_probe()
1014 if (IS_ERR(mt->thermal_base)) in mtk_thermal_probe()
1015 return PTR_ERR(mt->thermal_base); in mtk_thermal_probe()
1017 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); in mtk_thermal_probe()
1021 mutex_init(&mt->lock); in mtk_thermal_probe()
1023 mt->dev = &pdev->dev; in mtk_thermal_probe()
1025 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); in mtk_thermal_probe()
1027 dev_err(&pdev->dev, "missing auxadc node\n"); in mtk_thermal_probe()
1028 return -ENODEV; in mtk_thermal_probe()
1037 dev_err(&pdev->dev, "Can't get auxadc phys address\n"); in mtk_thermal_probe()
1038 return -EINVAL; in mtk_thermal_probe()
1041 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); in mtk_thermal_probe()
1043 dev_err(&pdev->dev, "missing apmixedsys node\n"); in mtk_thermal_probe()
1044 return -ENODEV; in mtk_thermal_probe()
1053 dev_err(&pdev->dev, "Can't get auxadc phys address\n"); in mtk_thermal_probe()
1054 return -EINVAL; in mtk_thermal_probe()
1057 ret = device_reset_optional(&pdev->dev); in mtk_thermal_probe()
1061 ret = clk_prepare_enable(mt->clk_auxadc); in mtk_thermal_probe()
1063 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); in mtk_thermal_probe()
1067 ret = clk_prepare_enable(mt->clk_peri_therm); in mtk_thermal_probe()
1069 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); in mtk_thermal_probe()
1073 if (mt->conf->version == MTK_THERMAL_V2) { in mtk_thermal_probe()
1078 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) in mtk_thermal_probe()
1079 for (i = 0; i < mt->conf->num_banks; i++) in mtk_thermal_probe()
1085 tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, in mtk_thermal_probe()
1094 dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); in mtk_thermal_probe()
1099 clk_disable_unprepare(mt->clk_peri_therm); in mtk_thermal_probe()
1101 clk_disable_unprepare(mt->clk_auxadc); in mtk_thermal_probe()
1110 clk_disable_unprepare(mt->clk_peri_therm); in mtk_thermal_remove()
1111 clk_disable_unprepare(mt->clk_auxadc); in mtk_thermal_remove()
1120 .name = "mtk-thermal",
1127 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1128 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1129 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1131 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1132 MODULE_DESCRIPTION("Mediatek thermal driver");